2 // Fix up trap and barrier handling.
3 // May want to have different statuses to differentiate the different stall
6 #ifndef __SIMPLE_RENAME_HH__
7 #define __SIMPLE_RENAME_HH__
11 #include "base/timebuf.hh"
13 // Will need rename maps for both the int reg file and fp reg file.
14 // Or change rename map class to handle both. (RegFile handles both.)
19 // Typedefs from the Impl.
20 typedef typename Impl::ISA ISA;
21 typedef typename Impl::CPUPol CPUPol;
22 typedef typename Impl::DynInstPtr DynInstPtr;
23 typedef typename Impl::FullCPU FullCPU;
24 typedef typename Impl::Params Params;
26 typedef typename CPUPol::FetchStruct FetchStruct;
27 typedef typename CPUPol::DecodeStruct DecodeStruct;
28 typedef typename CPUPol::RenameStruct RenameStruct;
29 typedef typename CPUPol::TimeStruct TimeStruct;
31 // Typedefs from the CPUPol
32 typedef typename CPUPol::FreeList FreeList;
33 typedef typename CPUPol::RenameMap RenameMap;
35 // Typedefs from the ISA.
36 typedef typename ISA::Addr Addr;
39 // Rename will block if ROB becomes full or issue queue becomes full,
40 // or there are no free registers to rename to.
41 // Only case where rename squashes is if IEW squashes.
55 SimpleRename(Params ¶ms);
57 void setCPU(FullCPU *cpu_ptr);
59 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
61 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
63 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
65 void setRenameMap(RenameMap *rm_ptr);
67 void setFreeList(FreeList *fl_ptr);
80 inline void unblock();
84 void removeFromHistory(InstSeqNum inst_seq_num);
86 inline void renameSrcRegs(DynInstPtr &inst);
88 inline void renameDestRegs(DynInstPtr &inst);
90 inline int calcFreeROBEntries();
92 inline int calcFreeIQEntries();
94 /** Holds the previous information for each rename.
95 * Note that often times the inst may have been deleted, so only access
96 * the pointer for the address and do not dereference it.
98 struct RenameHistory {
99 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
100 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
101 : instSeqNum(_instSeqNum), archReg(_archReg),
102 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
107 /** Constructor used specifically for cases where a place holder
108 * rename history entry is being made.
110 RenameHistory(InstSeqNum _instSeqNum)
111 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
112 prevPhysReg(0), placeHolder(true)
116 InstSeqNum instSeqNum;
118 PhysRegIndex newPhysReg;
119 PhysRegIndex prevPhysReg;
123 std::list<RenameHistory> historyBuffer;
125 /** CPU interface. */
128 // Interfaces to objects outside of rename.
129 /** Time buffer interface. */
130 TimeBuffer<TimeStruct> *timeBuffer;
132 /** Wire to get IEW's output from backwards time buffer. */
133 typename TimeBuffer<TimeStruct>::wire fromIEW;
135 /** Wire to get commit's output from backwards time buffer. */
136 typename TimeBuffer<TimeStruct>::wire fromCommit;
138 /** Wire to write infromation heading to previous stages. */
139 // Might not be the best name as not only decode will read it.
140 typename TimeBuffer<TimeStruct>::wire toDecode;
142 /** Rename instruction queue. */
143 TimeBuffer<RenameStruct> *renameQueue;
145 /** Wire to write any information heading to IEW. */
146 typename TimeBuffer<RenameStruct>::wire toIEW;
148 /** Decode instruction queue interface. */
149 TimeBuffer<DecodeStruct> *decodeQueue;
151 /** Wire to get decode's output from decode queue. */
152 typename TimeBuffer<DecodeStruct>::wire fromDecode;
154 /** Skid buffer between rename and decode. */
155 std::queue<DecodeStruct> skidBuffer;
157 /** Rename map interface. */
158 SimpleRenameMap *renameMap;
160 /** Free list interface. */
163 /** Delay between iew and rename, in ticks. */
164 int iewToRenameDelay;
166 /** Delay between decode and rename, in ticks. */
167 int decodeToRenameDelay;
169 /** Delay between commit and rename, in ticks. */
170 unsigned commitToRenameDelay;
172 /** Rename width, in instructions. */
173 unsigned renameWidth;
175 /** Commit width, in instructions. Used so rename knows how many
176 * instructions might have freed registers in the previous cycle.
178 unsigned commitWidth;
180 /** The instruction that rename is currently on. It needs to have
181 * persistent state so that when a stall occurs in the middle of a
182 * group of instructions, it can restart at the proper instruction.
187 #endif // __SIMPLE_RENAME_HH__