cd66ce68671cee629012af5230a25840614ad119
[gem5.git] / cpu / beta_cpu / rename.hh
1 // Todo:
2 // Figure out rename map for reg vs fp (probably just have one rename map).
3 // In simple case, there is no renaming, so have this stage do basically
4 // nothing.
5 // Fix up trap and barrier handling. Fix up squashing too, as it's too
6 // dependent upon the iew stage continually telling it to squash.
7 // Have commit send back information whenever a branch has committed. This
8 // way the history buffer can be cleared beyond the point where the branch
9 // was.
10
11 #ifndef __SIMPLE_RENAME_HH__
12 #define __SIMPLE_RENAME_HH__
13
14 //Will want to include: time buffer, structs, free list, rename map
15 #include <list>
16
17 #include "base/timebuf.hh"
18 #include "cpu/beta_cpu/comm.hh"
19 #include "cpu/beta_cpu/rename_map.hh"
20 #include "cpu/beta_cpu/free_list.hh"
21
22 using namespace std;
23
24 // Will need rename maps for both the int reg file and fp reg file.
25 // Or change rename map class to handle both. (RegFile handles both.)
26 template<class Impl>
27 class SimpleRename
28 {
29 public:
30 // Typedefs from the Impl.
31 typedef typename Impl::ISA ISA;
32 typedef typename Impl::CPUPol CPUPol;
33 typedef typename Impl::DynInst DynInst;
34 typedef typename Impl::FullCPU FullCPU;
35 typedef typename Impl::Params Params;
36
37 typedef typename Impl::FetchStruct FetchStruct;
38 typedef typename Impl::DecodeStruct DecodeStruct;
39 typedef typename Impl::RenameStruct RenameStruct;
40 typedef typename Impl::TimeStruct TimeStruct;
41
42 // Typedefs from the CPUPol
43 typedef typename CPUPol::FreeList FreeList;
44 typedef typename CPUPol::RenameMap RenameMap;
45
46 // Typedefs from the ISA.
47 typedef typename ISA::Addr Addr;
48
49 public:
50 // Rename will block if ROB becomes full or issue queue becomes full,
51 // or there are no free registers to rename to.
52 // Only case where rename squashes is if IEW squashes.
53 enum Status {
54 Running,
55 Idle,
56 Squashing,
57 Blocked,
58 Unblocking,
59 BarrierStall
60 };
61
62 private:
63 Status _status;
64
65 public:
66 SimpleRename(Params &params);
67
68 void setCPU(FullCPU *cpu_ptr);
69
70 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
71
72 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
73
74 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
75
76 void setRenameMap(RenameMap *rm_ptr);
77
78 void setFreeList(FreeList *fl_ptr);
79
80 void dumpHistory();
81
82 void tick();
83
84 void rename();
85
86 void squash();
87
88 private:
89 void block();
90
91 inline void unblock();
92
93 void doSquash();
94
95 void removeFromHistory(InstSeqNum inst_seq_num);
96
97 /** Holds the previous information for each rename.
98 * Note that often times the inst may have been deleted, so only access
99 * the pointer for the address and do not dereference it.
100 */
101 struct RenameHistory {
102 RenameHistory(InstSeqNum _instSeqNum, RegIndex _archReg,
103 PhysRegIndex _newPhysReg, PhysRegIndex _prevPhysReg)
104 : instSeqNum(_instSeqNum), archReg(_archReg),
105 newPhysReg(_newPhysReg), prevPhysReg(_prevPhysReg),
106 placeHolder(false)
107 {
108 }
109
110 /** Constructor used specifically for cases where a place holder
111 * rename history entry is being made.
112 */
113 RenameHistory(InstSeqNum _instSeqNum)
114 : instSeqNum(_instSeqNum), archReg(0), newPhysReg(0),
115 prevPhysReg(0), placeHolder(true)
116 {
117 }
118
119 InstSeqNum instSeqNum;
120 RegIndex archReg;
121 PhysRegIndex newPhysReg;
122 PhysRegIndex prevPhysReg;
123 bool placeHolder;
124 };
125
126 list<RenameHistory> historyBuffer;
127
128 /** CPU interface. */
129 FullCPU *cpu;
130
131 // Interfaces to objects outside of rename.
132 /** Time buffer interface. */
133 TimeBuffer<TimeStruct> *timeBuffer;
134
135 /** Wire to get IEW's output from backwards time buffer. */
136 typename TimeBuffer<TimeStruct>::wire fromIEW;
137
138 /** Wire to get commit's output from backwards time buffer. */
139 typename TimeBuffer<TimeStruct>::wire fromCommit;
140
141 /** Wire to write infromation heading to previous stages. */
142 // Might not be the best name as not only decode will read it.
143 typename TimeBuffer<TimeStruct>::wire toDecode;
144
145 /** Rename instruction queue. */
146 TimeBuffer<RenameStruct> *renameQueue;
147
148 /** Wire to write any information heading to IEW. */
149 typename TimeBuffer<RenameStruct>::wire toIEW;
150
151 /** Decode instruction queue interface. */
152 TimeBuffer<DecodeStruct> *decodeQueue;
153
154 /** Wire to get decode's output from decode queue. */
155 typename TimeBuffer<DecodeStruct>::wire fromDecode;
156
157 /** Skid buffer between rename and decode. */
158 queue<DecodeStruct> skidBuffer;
159
160 /** Rename map interface. */
161 SimpleRenameMap *renameMap;
162
163 /** Free list interface. */
164 FreeList *freeList;
165
166 /** Delay between iew and rename, in ticks. */
167 int iewToRenameDelay;
168
169 /** Delay between decode and rename, in ticks. */
170 int decodeToRenameDelay;
171
172 /** Delay between commit and rename, in ticks. */
173 unsigned commitToRenameDelay;
174
175 /** Rename width, in instructions. */
176 unsigned renameWidth;
177
178 /** Commit width, in instructions. Used so rename knows how many
179 * instructions might have freed registers in the previous cycle.
180 */
181 unsigned commitWidth;
182 };
183
184 #endif // __SIMPLE_RENAME_HH__