802944e47bf7617514a14efe24173d68a5ad8116
[gem5.git] / cpu / checker / cpu_builder.cc
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #include <string>
30
31 #include "cpu/checker/cpu.hh"
32 #include "cpu/inst_seq.hh"
33 #include "cpu/ozone/dyn_inst.hh"
34 #include "cpu/ozone/ozone_impl.hh"
35 #include "mem/base_mem.hh"
36 #include "sim/builder.hh"
37 #include "sim/process.hh"
38 #include "sim/sim_object.hh"
39
40 /**
41 * Specific non-templated derived class used for SimObject configuration.
42 */
43 class OzoneChecker : public Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >
44 {
45 public:
46 OzoneChecker(Params *p)
47 : Checker<RefCountingPtr<OzoneDynInst<OzoneImpl> > >(p)
48 { }
49 };
50
51 ////////////////////////////////////////////////////////////////////////
52 //
53 // CheckerCPU Simulation Object
54 //
55 BEGIN_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
56
57 Param<Counter> max_insts_any_thread;
58 Param<Counter> max_insts_all_threads;
59 Param<Counter> max_loads_any_thread;
60 Param<Counter> max_loads_all_threads;
61
62 #if FULL_SYSTEM
63 SimObjectParam<AlphaITB *> itb;
64 SimObjectParam<AlphaDTB *> dtb;
65 SimObjectParam<FunctionalMemory *> mem;
66 SimObjectParam<System *> system;
67 Param<int> cpu_id;
68 Param<Tick> profile;
69 #else
70 SimObjectParam<Process *> workload;
71 #endif // FULL_SYSTEM
72 Param<int> clock;
73 SimObjectParam<BaseMem *> icache;
74 SimObjectParam<BaseMem *> dcache;
75
76 Param<bool> defer_registration;
77 Param<bool> exitOnError;
78 Param<bool> updateOnError;
79 Param<bool> function_trace;
80 Param<Tick> function_trace_start;
81
82 END_DECLARE_SIM_OBJECT_PARAMS(OzoneChecker)
83
84 BEGIN_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
85
86 INIT_PARAM(max_insts_any_thread,
87 "terminate when any thread reaches this inst count"),
88 INIT_PARAM(max_insts_all_threads,
89 "terminate when all threads have reached this inst count"),
90 INIT_PARAM(max_loads_any_thread,
91 "terminate when any thread reaches this load count"),
92 INIT_PARAM(max_loads_all_threads,
93 "terminate when all threads have reached this load count"),
94
95 #if FULL_SYSTEM
96 INIT_PARAM(itb, "Instruction TLB"),
97 INIT_PARAM(dtb, "Data TLB"),
98 INIT_PARAM(mem, "memory"),
99 INIT_PARAM(system, "system object"),
100 INIT_PARAM(cpu_id, "processor ID"),
101 INIT_PARAM(profile, ""),
102 #else
103 INIT_PARAM(workload, "processes to run"),
104 #endif // FULL_SYSTEM
105
106 INIT_PARAM(clock, "clock speed"),
107 INIT_PARAM(icache, "L1 instruction cache object"),
108 INIT_PARAM(dcache, "L1 data cache object"),
109
110 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
111 INIT_PARAM(exitOnError, "exit on error"),
112 INIT_PARAM(updateOnError, "Update the checker with the main CPU's state on error"),
113 INIT_PARAM(function_trace, "Enable function trace"),
114 INIT_PARAM(function_trace_start, "Cycle to start function trace")
115
116 END_INIT_SIM_OBJECT_PARAMS(OzoneChecker)
117
118
119 CREATE_SIM_OBJECT(OzoneChecker)
120 {
121 OzoneChecker::Params *params = new OzoneChecker::Params();
122 params->name = getInstanceName();
123 params->numberOfThreads = 1;
124 params->max_insts_any_thread = 0;
125 params->max_insts_all_threads = 0;
126 params->max_loads_any_thread = 0;
127 params->max_loads_all_threads = 0;
128 params->exitOnError = exitOnError;
129 params->updateOnError = updateOnError;
130 params->deferRegistration = defer_registration;
131 params->functionTrace = function_trace;
132 params->functionTraceStart = function_trace_start;
133 params->clock = clock;
134 // Hack to touch all parameters. Consider not deriving Checker
135 // from BaseCPU..it's not really a CPU in the end.
136 Counter temp;
137 temp = max_insts_any_thread;
138 temp = max_insts_all_threads;
139 temp = max_loads_any_thread;
140 temp = max_loads_all_threads;
141 BaseMem *cache = icache;
142 cache = dcache;
143
144 #if FULL_SYSTEM
145 params->itb = itb;
146 params->dtb = dtb;
147 params->mem = mem;
148 params->system = system;
149 params->cpu_id = cpu_id;
150 params->profile = profile;
151 #else
152 params->process = workload;
153 #endif
154
155 OzoneChecker *cpu = new OzoneChecker(params);
156 return cpu;
157 }
158
159 REGISTER_SIM_OBJECT("OzoneChecker", OzoneChecker)