125bfa398f83fdeee6d10ee2c2480ddbc4d0bffc
[gem5.git] / cpu / checker / o3_cpu_builder.cc
1
2 #include <string>
3
4 #include "cpu/checker/cpu.hh"
5 #include "cpu/inst_seq.hh"
6 #include "cpu/o3/alpha_dyn_inst.hh"
7 #include "cpu/o3/alpha_impl.hh"
8 #include "mem/base_mem.hh"
9 #include "sim/builder.hh"
10 #include "sim/process.hh"
11 #include "sim/sim_object.hh"
12
13 class O3Checker : public Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >
14 {
15 public:
16 O3Checker(Params *p)
17 : Checker<RefCountingPtr<AlphaDynInst<AlphaSimpleImpl> > >(p)
18 { }
19 };
20
21 ////////////////////////////////////////////////////////////////////////
22 //
23 // CheckerCPU Simulation Object
24 //
25 BEGIN_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
26
27 Param<Counter> max_insts_any_thread;
28 Param<Counter> max_insts_all_threads;
29 Param<Counter> max_loads_any_thread;
30 Param<Counter> max_loads_all_threads;
31
32 #if FULL_SYSTEM
33 SimObjectParam<AlphaITB *> itb;
34 SimObjectParam<AlphaDTB *> dtb;
35 SimObjectParam<FunctionalMemory *> mem;
36 SimObjectParam<System *> system;
37 Param<int> cpu_id;
38 Param<Tick> profile;
39 #else
40 SimObjectParam<Process *> workload;
41 #endif // FULL_SYSTEM
42 Param<int> clock;
43 SimObjectParam<BaseMem *> icache;
44 SimObjectParam<BaseMem *> dcache;
45
46 Param<bool> defer_registration;
47 Param<bool> exitOnError;
48 Param<bool> function_trace;
49 Param<Tick> function_trace_start;
50
51 END_DECLARE_SIM_OBJECT_PARAMS(O3Checker)
52
53 BEGIN_INIT_SIM_OBJECT_PARAMS(O3Checker)
54
55 INIT_PARAM(max_insts_any_thread,
56 "terminate when any thread reaches this inst count"),
57 INIT_PARAM(max_insts_all_threads,
58 "terminate when all threads have reached this inst count"),
59 INIT_PARAM(max_loads_any_thread,
60 "terminate when any thread reaches this load count"),
61 INIT_PARAM(max_loads_all_threads,
62 "terminate when all threads have reached this load count"),
63
64 #if FULL_SYSTEM
65 INIT_PARAM(itb, "Instruction TLB"),
66 INIT_PARAM(dtb, "Data TLB"),
67 INIT_PARAM(mem, "memory"),
68 INIT_PARAM(system, "system object"),
69 INIT_PARAM(cpu_id, "processor ID"),
70 INIT_PARAM(profile, ""),
71 #else
72 INIT_PARAM(workload, "processes to run"),
73 #endif // FULL_SYSTEM
74
75 INIT_PARAM(clock, "clock speed"),
76 INIT_PARAM(icache, "L1 instruction cache object"),
77 INIT_PARAM(dcache, "L1 data cache object"),
78
79 INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
80 INIT_PARAM(exitOnError, "exit on error"),
81 INIT_PARAM(function_trace, "Enable function trace"),
82 INIT_PARAM(function_trace_start, "Cycle to start function trace")
83
84 END_INIT_SIM_OBJECT_PARAMS(O3Checker)
85
86
87 CREATE_SIM_OBJECT(O3Checker)
88 {
89 O3Checker::Params *params = new O3Checker::Params();
90 params->name = getInstanceName();
91 params->numberOfThreads = 1;
92 params->max_insts_any_thread = 0;
93 params->max_insts_all_threads = 0;
94 params->max_loads_any_thread = 0;
95 params->max_loads_all_threads = 0;
96 params->exitOnError = exitOnError;
97 params->deferRegistration = defer_registration;
98 params->functionTrace = function_trace;
99 params->functionTraceStart = function_trace_start;
100 params->clock = clock;
101 // Hack to touch all parameters. Consider not deriving Checker
102 // from BaseCPU..it's not really a CPU in the end.
103 Counter temp;
104 temp = max_insts_any_thread;
105 temp = max_insts_all_threads;
106 temp = max_loads_any_thread;
107 temp = max_loads_all_threads;
108 BaseMem *cache = icache;
109 cache = dcache;
110
111 #if FULL_SYSTEM
112 params->itb = itb;
113 params->dtb = dtb;
114 params->mem = mem;
115 params->system = system;
116 params->cpu_id = cpu_id;
117 params->profile = profile;
118 #else
119 params->process = workload;
120 #endif
121
122 O3Checker *cpu = new O3Checker(params);
123 return cpu;
124 }
125
126 REGISTER_SIM_OBJECT("O3Checker", O3Checker)