cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
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   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
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   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_EXEC_CONTEXT_HH__
  30 #define __CPU_EXEC_CONTEXT_HH__
  31
  32 #include "config/full_system.hh"
  33 #include "mem/functional/functional.hh"
  34 #include "mem/mem_req.hh"
  35 #include "sim/host.hh"
  36 #include "sim/serialize.hh"
  37 #include "arch/isa_traits.hh"
  38 //#include "arch/isa_registers.hh"
  39 #include "sim/byteswap.hh"
  40
  41 // forward declaration: see functional_memory.hh
  42 class FunctionalMemory;
  43 class PhysicalMemory;
  44 class BaseCPU;
  45
  46 #if FULL_SYSTEM
  47
  48 #include "sim/system.hh"
  49 #include "targetarch/alpha_memory.hh"
  50
  51 class FunctionProfile;
  52 class ProfileNode;
  53 class MemoryController;
  54 namespace Kernel { class Binning; class Statistics; }
  55
  56 #else // !FULL_SYSTEM
  57
  58 #include "sim/process.hh"
  59
  60 #endif // FULL_SYSTEM
  61
  62 //
  63 // The ExecContext object represents a functional context for
  64 // instruction execution.  It incorporates everything required for
  65 // architecture-level functional simulation of a single thread.
  66 //
  67
  68 class ExecContext
  69 {
  70   protected:
  71     typedef TheISA::RegFile RegFile;
  72     typedef TheISA::Addr Addr;
  73     typedef TheISA::MachInst MachInst;
  74     typedef TheISA::MiscRegFile MiscRegFile;
  75   public:
  76     enum Status
  77     {
  78         /// Initialized but not running yet.  All CPUs start in
  79         /// this state, but most transition to Active on cycle 1.
  80         /// In MP or SMT systems, non-primary contexts will stay
  81         /// in this state until a thread is assigned to them.
  82         Unallocated,
  83
  84         /// Running.  Instructions should be executed only when
  85         /// the context is in this state.
  86         Active,
  87
  88         /// Temporarily inactive.  Entered while waiting for
  89         /// initialization,synchronization, etc.
  90         Suspended,
  91
  92         /// Permanently shut down.  Entered when target executes
  93         /// m5exit pseudo-instruction.  When all contexts enter
  94         /// this state, the simulation will terminate.
  95         Halted
  96     };
  97
  98   private:
  99     Status _status;
 100
 101   public:
 102     Status status() const { return _status; }
 103
 104     void setStatus(Status newStatus) { _status = newStatus; }
 105
 106     /// Set the status to Active.  Optional delay indicates number of
 107     /// cycles to wait before beginning execution.
 108     void activate(int delay = 1);
 109
 110     /// Set the status to Suspended.
 111     void suspend();
 112
 113     /// Set the status to Unallocated.
 114     void deallocate();
 115
 116     /// Set the status to Halted.
 117     void halt();
 118
 119   public:
 120     RegFile regs;       // correct-path register context
 121
 122     // pointer to CPU associated with this context
 123     BaseCPU *cpu;
 124
 125     // Current instruction
 126     MachInst inst;
 127
 128     // Index of hardware thread context on the CPU that this represents.
 129     int thread_num;
 130
 131     // ID of this context w.r.t. the System or Process object to which
 132     // it belongs.  For full-system mode, this is the system CPU ID.
 133     int cpu_id;
 134
 135 #if FULL_SYSTEM
 136     FunctionalMemory *mem;
 137     AlphaITB *itb;
 138     AlphaDTB *dtb;
 139     System *system;
 140
 141     // the following two fields are redundant, since we can always
 142     // look them up through the system pointer, but we'll leave them
 143     // here for now for convenience
 144     MemoryController *memctrl;
 145     PhysicalMemory *physmem;
 146
 147     Kernel::Binning *kernelBinning;
 148     Kernel::Statistics *kernelStats;
 149     bool bin;
 150     bool fnbin;
 151
 152     FunctionProfile *profile;
 153     ProfileNode *profileNode;
 154     Addr profilePC;
 155     void dumpFuncProfile();
 156
 157 #else
 158     Process *process;
 159
 160     FunctionalMemory *mem;      // functional storage for process address space
 161
 162     // Address space ID.  Note that this is used for TIMING cache
 163     // simulation only; all functional memory accesses should use
 164     // one of the FunctionalMemory pointers above.
 165     short asid;
 166
 167 #endif
 168
 169     /**
 170      * Temporary storage to pass the source address from copy_load to
 171      * copy_store.
 172      * @todo Remove this temporary when we have a better way to do it.
 173      */
 174     Addr copySrcAddr;
 175     /**
 176      * Temp storage for the physical source address of a copy.
 177      * @todo Remove this temporary when we have a better way to do it.
 178      */
 179     Addr copySrcPhysAddr;
 180
 181
 182     /*
 183      * number of executed instructions, for matching with syscall trace
 184      * points in EIO files.
 185      */
 186     Counter func_exe_inst;
 187
 188     //
 189     // Count failed store conditionals so we can warn of apparent
 190     // application deadlock situations.
 191     unsigned storeCondFailures;
 192
 193     // constructor: initialize context from given process structure
 194 #if FULL_SYSTEM
 195     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 196                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 197 #else
 198     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 199     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 200                 int _asid);
 201 #endif
 202     virtual ~ExecContext();
 203
 204     virtual void takeOverFrom(ExecContext *oldContext);
 205
 206     void regStats(const std::string &name);
 207
 208     void serialize(std::ostream &os);
 209     void unserialize(Checkpoint *cp, const std::string &section);
 210
 211 #if FULL_SYSTEM
 212     bool validInstAddr(Addr addr) { return true; }
 213     bool validDataAddr(Addr addr) { return true; }
 214     int getInstAsid() { return regs.instAsid(); }
 215     int getDataAsid() { return regs.dataAsid(); }
 216
 217     Fault * translateInstReq(MemReqPtr &req)
 218     {
 219         return itb->translate(req);
 220     }
 221
 222     Fault * translateDataReadReq(MemReqPtr &req)
 223     {
 224         return dtb->translate(req, false);
 225     }
 226
 227     Fault * translateDataWriteReq(MemReqPtr &req)
 228     {
 229         return dtb->translate(req, true);
 230     }
 231
 232 #else
 233     bool validInstAddr(Addr addr)
 234     { return process->validInstAddr(addr); }
 235
 236     bool validDataAddr(Addr addr)
 237     { return process->validDataAddr(addr); }
 238
 239     int getInstAsid() { return asid; }
 240     int getDataAsid() { return asid; }
 241
 242     Fault * dummyTranslation(MemReqPtr &req)
 243     {
 244 #if 0
 245         assert((req->vaddr >> 48 & 0xffff) == 0);
 246 #endif
 247
 248         // put the asid in the upper 16 bits of the paddr
 249         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 250         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 251         return NoFault;
 252     }
 253     Fault * translateInstReq(MemReqPtr &req)
 254     {
 255         return dummyTranslation(req);
 256     }
 257     Fault * translateDataReadReq(MemReqPtr &req)
 258     {
 259         return dummyTranslation(req);
 260     }
 261     Fault * translateDataWriteReq(MemReqPtr &req)
 262     {
 263         return dummyTranslation(req);
 264     }
 265
 266 #endif
 267
 268     template <class T>
 269     Fault * read(MemReqPtr &req, T &data)
 270     {
 271 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 272         if (req->flags & LOCKED) {
 273             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 274             cregs->lock_addr = req->paddr;
 275             cregs->lock_flag = true;
 276         }
 277 #endif
 278
 279         Fault * error;
 280         error = mem->read(req, data);
 281         data = LittleEndianGuest::gtoh(data);
 282         return error;
 283     }
 284
 285     template <class T>
 286     Fault * write(MemReqPtr &req, T &data)
 287     {
 288 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 289
 290         MiscRegFile *cregs;
 291
 292         // If this is a store conditional, act appropriately
 293         if (req->flags & LOCKED) {
 294             cregs = &req->xc->regs.miscRegs;
 295
 296             if (req->flags & UNCACHEABLE) {
 297                 // Don't update result register (see stq_c in isa_desc)
 298                 req->result = 2;
 299                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 300             } else {
 301                 req->result = cregs->lock_flag;
 302                 if (!cregs->lock_flag ||
 303                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 304                     cregs->lock_flag = false;
 305                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 306                         std::cerr << "Warning: "
 307                                   << req->xc->storeCondFailures
 308                                   << " consecutive store conditional failures "
 309                                   << "on cpu " << req->xc->cpu_id
 310                                   << std::endl;
 311                     }
 312                     return NoFault;
 313                 }
 314                 else req->xc->storeCondFailures = 0;
 315             }
 316         }
 317
 318         // Need to clear any locked flags on other proccessors for
 319         // this address.  Only do this for succsful Store Conditionals
 320         // and all other stores (WH64?).  Unsuccessful Store
 321         // Conditionals would have returned above, and wouldn't fall
 322         // through.
 323         for (int i = 0; i < system->execContexts.size(); i++){
 324             cregs = &system->execContexts[i]->regs.miscRegs;
 325             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 326                 cregs->lock_flag = false;
 327             }
 328         }
 329
 330 #endif
 331         return mem->write(req, (T)LittleEndianGuest::htog(data));
 332     }
 333
 334     virtual bool misspeculating();
 335
 336
 337     MachInst getInst() { return inst; }
 338
 339     void setInst(MachInst new_inst)
 340     {
 341         inst = new_inst;
 342     }
 343
 344     Fault * instRead(MemReqPtr &req)
 345     {
 346         return mem->read(req, inst);
 347     }
 348
 349     //
 350     // New accessors for new decoder.
 351     //
 352     uint64_t readIntReg(int reg_idx)
 353     {
 354         return regs.intRegFile[reg_idx];
 355     }
 356
 357     float readFloatRegSingle(int reg_idx)
 358     {
 359         return (float)regs.floatRegFile.d[reg_idx];
 360     }
 361
 362     double readFloatRegDouble(int reg_idx)
 363     {
 364         return regs.floatRegFile.d[reg_idx];
 365     }
 366
 367     uint64_t readFloatRegInt(int reg_idx)
 368     {
 369         return regs.floatRegFile.q[reg_idx];
 370     }
 371
 372     void setIntReg(int reg_idx, uint64_t val)
 373     {
 374         regs.intRegFile[reg_idx] = val;
 375     }
 376
 377     void setFloatRegSingle(int reg_idx, float val)
 378     {
 379         regs.floatRegFile.d[reg_idx] = (double)val;
 380     }
 381
 382     void setFloatRegDouble(int reg_idx, double val)
 383     {
 384         regs.floatRegFile.d[reg_idx] = val;
 385     }
 386
 387     void setFloatRegInt(int reg_idx, uint64_t val)
 388     {
 389         regs.floatRegFile.q[reg_idx] = val;
 390     }
 391
 392     uint64_t readPC()
 393     {
 394         return regs.pc;
 395     }
 396
 397     void setNextPC(uint64_t val)
 398     {
 399         regs.npc = val;
 400     }
 401
 402     uint64_t readUniq()
 403     {
 404         return regs.miscRegs.uniq;
 405     }
 406
 407     void setUniq(uint64_t val)
 408     {
 409         regs.miscRegs.uniq = val;
 410     }
 411
 412     uint64_t readFpcr()
 413     {
 414         return regs.miscRegs.fpcr;
 415     }
 416
 417     void setFpcr(uint64_t val)
 418     {
 419         regs.miscRegs.fpcr = val;
 420     }
 421
 422 #if FULL_SYSTEM
 423     uint64_t readIpr(int idx, Fault * &fault);
 424     Fault * setIpr(int idx, uint64_t val);
 425     int readIntrFlag() { return regs.intrflag; }
 426     void setIntrFlag(int val) { regs.intrflag = val; }
 427     Fault * hwrei();
 428     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
 429     void ev5_trap(Fault * fault);
 430     bool simPalCheck(int palFunc);
 431 #endif
 432
 433     /** Meant to be more generic trap function to be
 434      *  called when an instruction faults.
 435      *  @param fault The fault generated by executing the instruction.
 436      *  @todo How to do this properly so it's dependent upon ISA only?
 437      */
 438
 439     void trap(Fault * fault);
 440
 441 #if !FULL_SYSTEM
 442     TheISA::IntReg getSyscallArg(int i)
 443     {
 444         return regs.intRegFile[TheISA::ArgumentReg0 + i];
 445     }
 446
 447     // used to shift args for indirect syscall
 448     void setSyscallArg(int i, TheISA::IntReg val)
 449     {
 450         regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
 451     }
 452
 453     void setSyscallReturn(SyscallReturn return_value)
 454     {
 455         // check for error condition.  Alpha syscall convention is to
 456         // indicate success/failure in reg a3 (r19) and put the
 457         // return value itself in the standard return value reg (v0).
 458         const int RegA3 = 19;   // only place this is used
 459         if (return_value.successful()) {
 460             // no error
 461             regs.intRegFile[RegA3] = 0;
 462             regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
 463         } else {
 464             // got an error, return details
 465             regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
 466             regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
 467         }
 468     }
 469
 470     void syscall()
 471     {
 472         process->syscall(this);
 473     }
 474 #endif
 475 };
 476
 477
 478 // for non-speculative execution context, spec_mode is always false
 479 inline bool
 480 ExecContext::misspeculating()
 481 {
 482     return false;
 483 }
 484
 485 #endif // __CPU_EXEC_CONTEXT_HH__