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29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "targetarch/mem_req.hh"
35 // forward declaration: see functional_memory.hh
36 class FunctionalMemory;
42 #include "targetarch/alpha_memory.hh"
43 class MemoryController;
45 #include "kern/tru64/kernel_stats.hh"
46 #include "sim/system.hh"
50 #include "sim/prog.hh"
55 // The ExecContext object represents a functional context for
56 // instruction execution. It incorporates everything required for
57 // architecture-level functional simulation of a single thread.
63 enum Status { Unallocated, Active, Suspended, Halted };
69 Status status() const { return _status; }
70 void setStatus(Status new_status);
74 KernelStats kernelStats;
78 RegFile regs; // correct-path register context
80 // pointer to CPU associated with this context
83 // Index of hardware thread context on the CPU that this represents.
88 FunctionalMemory *mem;
94 // the following two fields are redundant, since we can always
95 // look them up through the system pointer, but we'll leave them
96 // here for now for convenience
97 MemoryController *memCtrl;
98 PhysicalMemory *physmem;
103 FunctionalMemory *mem; // functional storage for process address space
105 // Address space ID. Note that this is used for TIMING cache
106 // simulation only; all functional memory accesses should use
107 // one of the FunctionalMemory pointers above.
114 * number of executed instructions, for matching with syscall trace
115 * points in EIO files.
117 Counter func_exe_insn;
120 // Count failed store conditionals so we can warn of apparent
121 // application deadlock situations.
122 unsigned storeCondFailures;
124 // constructor: initialize context from given process structure
126 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
127 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem,
130 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
131 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
134 virtual ~ExecContext() {}
136 void regStats(const std::string &name);
139 bool validInstAddr(Addr addr) { return true; }
140 bool validDataAddr(Addr addr) { return true; }
141 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
142 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
144 Fault translateInstReq(MemReqPtr req)
146 return itb->translate(req);
149 Fault translateDataReadReq(MemReqPtr req)
151 return dtb->translate(req, false);
154 Fault translateDataWriteReq(MemReqPtr req)
156 return dtb->translate(req, true);
161 bool validInstAddr(Addr addr)
162 { return process->validInstAddr(addr); }
164 bool validDataAddr(Addr addr)
165 { return process->validDataAddr(addr); }
167 int getInstAsid() { return asid; }
168 int getDataAsid() { return asid; }
170 Fault dummyTranslation(MemReqPtr req)
173 assert((req->vaddr >> 48 & 0xffff) == 0);
176 // put the asid in the upper 16 bits of the paddr
177 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
178 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
181 Fault translateInstReq(MemReqPtr req)
183 return dummyTranslation(req);
185 Fault translateDataReadReq(MemReqPtr req)
187 return dummyTranslation(req);
189 Fault translateDataWriteReq(MemReqPtr req)
191 return dummyTranslation(req);
197 Fault read(MemReqPtr req, T& data)
199 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
200 if (req->flags & LOCKED) {
201 MiscRegFile *cregs = &req->xc->regs.miscRegs;
202 cregs->lock_addr = req->paddr;
203 cregs->lock_flag = true;
206 return mem->read(req, data);
210 Fault write(MemReqPtr req, T& data)
212 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
216 // If this is a store conditional, act appropriately
217 if (req->flags & LOCKED) {
218 cregs = &req->xc->regs.miscRegs;
220 if (req->flags & UNCACHEABLE) {
221 // Don't update result register (see machine.def)
223 req->xc->storeCondFailures = 0;//Needed? [RGD]
225 req->result = cregs->lock_flag;
226 if (!cregs->lock_flag ||
227 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
228 cregs->lock_flag = false;
229 if (((++req->xc->storeCondFailures) % 100000) == 0) {
230 std::cerr << "Warning: "
231 << req->xc->storeCondFailures
232 << " consecutive store conditional failures "
233 << "on cpu " << req->xc->cpu_id
238 else req->xc->storeCondFailures = 0;
242 // Need to clear any locked flags on other proccessors for this
244 // Only do this for succsful Store Conditionals and all other
246 // Unsuccesful Store Conditionals would have returned above,
247 // and wouldn't fall through
248 for(int i = 0; i < system->num_cpus; i++){
249 cregs = &system->xc_array[i]->regs.miscRegs;
250 if((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
251 cregs->lock_flag = false;
256 return mem->write(req, data);
259 virtual bool misspeculating();
263 // New accessors for new decoder.
265 uint64_t readIntReg(int reg_idx)
267 return regs.intRegFile[reg_idx];
270 float readFloatRegSingle(int reg_idx)
272 return (float)regs.floatRegFile.d[reg_idx];
275 double readFloatRegDouble(int reg_idx)
277 return regs.floatRegFile.d[reg_idx];
280 uint64_t readFloatRegInt(int reg_idx)
282 return regs.floatRegFile.q[reg_idx];
285 void setIntReg(int reg_idx, uint64_t val)
287 regs.intRegFile[reg_idx] = val;
290 void setFloatRegSingle(int reg_idx, float val)
292 regs.floatRegFile.d[reg_idx] = (double)val;
295 void setFloatRegDouble(int reg_idx, double val)
297 regs.floatRegFile.d[reg_idx] = val;
300 void setFloatRegInt(int reg_idx, uint64_t val)
302 regs.floatRegFile.q[reg_idx] = val;
310 void setNextPC(uint64_t val)
317 return regs.miscRegs.uniq;
320 void setUniq(uint64_t val)
322 regs.miscRegs.uniq = val;
327 return regs.miscRegs.fpcr;
330 void setFpcr(uint64_t val)
332 regs.miscRegs.fpcr = val;
336 uint64_t readIpr(int idx, Fault &fault);
337 Fault setIpr(int idx, uint64_t val);
339 void ev5_trap(Fault fault);
340 bool simPalCheck(int palFunc);
346 process->syscall(this);
352 // for non-speculative execution context, spec_mode is always false
354 ExecContext::misspeculating()
359 #endif // __EXEC_CONTEXT_HH__