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29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "mem/mem_req.hh"
34 #include "sim/serialize.hh"
36 // forward declaration: see functional_memory.hh
37 class FunctionalMemory;
43 #include "targetarch/alpha_memory.hh"
44 class MemoryController;
46 #include "kern/tru64/kernel_stats.hh"
47 #include "sim/system.hh"
48 #include "sim/sw_context.hh"
52 #include "sim/process.hh"
57 // The ExecContext object represents a functional context for
58 // instruction execution. It incorporates everything required for
59 // architecture-level functional simulation of a single thread.
67 /// Initialized but not running yet. All CPUs start in
68 /// this state, but most transition to Active on cycle 1.
69 /// In MP or SMT systems, non-primary contexts will stay
70 /// in this state until a thread is assigned to them.
73 /// Running. Instructions should be executed only when
74 /// the context is in this state.
77 /// Temporarily inactive. Entered while waiting for
78 /// synchronization, etc.
81 /// Permanently shut down. Entered when target executes
82 /// m5exit pseudo-instruction. When all contexts enter
83 /// this state, the simulation will terminate.
91 Status status() const { return _status; }
93 /// Set the status to Active. Optional delay indicates number of
94 /// cycles to wait before beginning execution.
95 void activate(int delay = 1);
97 /// Set the status to Suspended.
100 /// Set the status to Unallocated.
103 /// Set the status to Halted.
108 KernelStats kernelStats;
112 RegFile regs; // correct-path register context
114 // pointer to CPU associated with this context
117 // Index of hardware thread context on the CPU that this represents.
120 // ID of this context w.r.t. the System or Process object to which
121 // it belongs. For full-system mode, this is the system CPU ID.
126 FunctionalMemory *mem;
131 // the following two fields are redundant, since we can always
132 // look them up through the system pointer, but we'll leave them
133 // here for now for convenience
134 MemoryController *memCtrl;
135 PhysicalMemory *physmem;
141 FunctionalMemory *mem; // functional storage for process address space
143 // Address space ID. Note that this is used for TIMING cache
144 // simulation only; all functional memory accesses should use
145 // one of the FunctionalMemory pointers above.
151 * Temporary storage to pass the source address from copy_load to
153 * @todo Remove this temporary when we have a better way to do it.
157 * Temp storage for the physical source address of a copy.
158 * @todo Remove this temporary when we have a better way to do it.
160 Addr copySrcPhysAddr;
164 * number of executed instructions, for matching with syscall trace
165 * points in EIO files.
167 Counter func_exe_inst;
170 // Count failed store conditionals so we can warn of apparent
171 // application deadlock situations.
172 unsigned storeCondFailures;
174 // constructor: initialize context from given process structure
176 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
177 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
179 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
180 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
183 virtual ~ExecContext() {}
185 virtual void takeOverFrom(ExecContext *oldContext);
187 void regStats(const std::string &name);
189 void serialize(std::ostream &os);
190 void unserialize(Checkpoint *cp, const std::string §ion);
193 bool validInstAddr(Addr addr) { return true; }
194 bool validDataAddr(Addr addr) { return true; }
195 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
196 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
198 Fault translateInstReq(MemReqPtr &req)
200 return itb->translate(req);
203 Fault translateDataReadReq(MemReqPtr &req)
205 return dtb->translate(req, false);
208 Fault translateDataWriteReq(MemReqPtr &req)
210 return dtb->translate(req, true);
214 bool validInstAddr(Addr addr)
215 { return process->validInstAddr(addr); }
217 bool validDataAddr(Addr addr)
218 { return process->validDataAddr(addr); }
220 int getInstAsid() { return asid; }
221 int getDataAsid() { return asid; }
223 Fault dummyTranslation(MemReqPtr &req)
226 assert((req->vaddr >> 48 & 0xffff) == 0);
229 // put the asid in the upper 16 bits of the paddr
230 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
231 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
234 Fault translateInstReq(MemReqPtr &req)
236 return dummyTranslation(req);
238 Fault translateDataReadReq(MemReqPtr &req)
240 return dummyTranslation(req);
242 Fault translateDataWriteReq(MemReqPtr &req)
244 return dummyTranslation(req);
250 Fault read(MemReqPtr &req, T &data)
252 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
253 if (req->flags & LOCKED) {
254 MiscRegFile *cregs = &req->xc->regs.miscRegs;
255 cregs->lock_addr = req->paddr;
256 cregs->lock_flag = true;
259 return mem->read(req, data);
263 Fault write(MemReqPtr &req, T &data)
265 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
269 // If this is a store conditional, act appropriately
270 if (req->flags & LOCKED) {
271 cregs = &req->xc->regs.miscRegs;
273 if (req->flags & UNCACHEABLE) {
274 // Don't update result register (see stq_c in isa_desc)
276 req->xc->storeCondFailures = 0;//Needed? [RGD]
278 req->result = cregs->lock_flag;
279 if (!cregs->lock_flag ||
280 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
281 cregs->lock_flag = false;
282 if (((++req->xc->storeCondFailures) % 100000) == 0) {
283 std::cerr << "Warning: "
284 << req->xc->storeCondFailures
285 << " consecutive store conditional failures "
286 << "on cpu " << req->xc->cpu_id
291 else req->xc->storeCondFailures = 0;
295 // Need to clear any locked flags on other proccessors for
296 // this address. Only do this for succsful Store Conditionals
297 // and all other stores (WH64?). Unsuccessful Store
298 // Conditionals would have returned above, and wouldn't fall
300 for (int i = 0; i < system->execContexts.size(); i++){
301 cregs = &system->execContexts[i]->regs.miscRegs;
302 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
303 cregs->lock_flag = false;
308 return mem->write(req, data);
311 virtual bool misspeculating();
315 // New accessors for new decoder.
317 uint64_t readIntReg(int reg_idx)
319 return regs.intRegFile[reg_idx];
322 float readFloatRegSingle(int reg_idx)
324 return (float)regs.floatRegFile.d[reg_idx];
327 double readFloatRegDouble(int reg_idx)
329 return regs.floatRegFile.d[reg_idx];
332 uint64_t readFloatRegInt(int reg_idx)
334 return regs.floatRegFile.q[reg_idx];
337 void setIntReg(int reg_idx, uint64_t val)
339 regs.intRegFile[reg_idx] = val;
342 void setFloatRegSingle(int reg_idx, float val)
344 regs.floatRegFile.d[reg_idx] = (double)val;
347 void setFloatRegDouble(int reg_idx, double val)
349 regs.floatRegFile.d[reg_idx] = val;
352 void setFloatRegInt(int reg_idx, uint64_t val)
354 regs.floatRegFile.q[reg_idx] = val;
362 void setNextPC(uint64_t val)
369 return regs.miscRegs.uniq;
372 void setUniq(uint64_t val)
374 regs.miscRegs.uniq = val;
379 return regs.miscRegs.fpcr;
382 void setFpcr(uint64_t val)
384 regs.miscRegs.fpcr = val;
388 uint64_t readIpr(int idx, Fault &fault);
389 Fault setIpr(int idx, uint64_t val);
390 int readIntrFlag() { return regs.intrflag; }
391 void setIntrFlag(int val) { regs.intrflag = val; }
393 bool inPalMode() { return PC_PAL(regs.pc); }
394 void ev5_trap(Fault fault);
395 bool simPalCheck(int palFunc);
399 IntReg getSyscallArg(int i)
401 return regs.intRegFile[ArgumentReg0 + i];
404 // used to shift args for indirect syscall
405 void setSyscallArg(int i, IntReg val)
407 regs.intRegFile[ArgumentReg0 + i] = val;
410 void setSyscallReturn(int64_t return_value)
412 // check for error condition. Alpha syscall convention is to
413 // indicate success/failure in reg a3 (r19) and put the
414 // return value itself in the standard return value reg (v0).
415 const int RegA3 = 19; // only place this is used
416 if (return_value >= 0) {
418 regs.intRegFile[RegA3] = 0;
419 regs.intRegFile[ReturnValueReg] = return_value;
421 // got an error, return details
422 regs.intRegFile[RegA3] = (IntReg) -1;
423 regs.intRegFile[ReturnValueReg] = -return_value;
429 process->syscall(this);
435 // for non-speculative execution context, spec_mode is always false
437 ExecContext::misspeculating()
442 #endif // __EXEC_CONTEXT_HH__