2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "mem/mem_req.hh"
34 #include "mem/functional_mem/functional_memory.hh"
35 #include "sim/serialize.hh"
36 #include "targetarch/byte_swap.hh"
38 // forward declaration: see functional_memory.hh
39 class FunctionalMemory;
45 #include "sim/system.hh"
46 #include "targetarch/alpha_memory.hh"
48 class MemoryController;
50 namespace Kernel { class Binning; class Statistics; }
54 #include "sim/process.hh"
59 // The ExecContext object represents a functional context for
60 // instruction execution. It incorporates everything required for
61 // architecture-level functional simulation of a single thread.
69 /// Initialized but not running yet. All CPUs start in
70 /// this state, but most transition to Active on cycle 1.
71 /// In MP or SMT systems, non-primary contexts will stay
72 /// in this state until a thread is assigned to them.
75 /// Running. Instructions should be executed only when
76 /// the context is in this state.
79 /// Temporarily inactive. Entered while waiting for
80 /// synchronization, etc.
83 /// Permanently shut down. Entered when target executes
84 /// m5exit pseudo-instruction. When all contexts enter
85 /// this state, the simulation will terminate.
93 Status status() const { return _status; }
95 /// Set the status to Active. Optional delay indicates number of
96 /// cycles to wait before beginning execution.
97 void activate(int delay = 1);
99 /// Set the status to Suspended.
102 /// Set the status to Unallocated.
105 /// Set the status to Halted.
109 RegFile regs; // correct-path register context
111 // pointer to CPU associated with this context
114 // Current instruction
117 // Index of hardware thread context on the CPU that this represents.
120 // ID of this context w.r.t. the System or Process object to which
121 // it belongs. For full-system mode, this is the system CPU ID.
125 FunctionalMemory *mem;
130 // the following two fields are redundant, since we can always
131 // look them up through the system pointer, but we'll leave them
132 // here for now for convenience
133 MemoryController *memctrl;
134 PhysicalMemory *physmem;
136 Kernel::Binning *kernelBinning;
137 Kernel::Statistics *kernelStats;
140 void execute(const StaticInstBase *inst);
145 FunctionalMemory *mem; // functional storage for process address space
147 // Address space ID. Note that this is used for TIMING cache
148 // simulation only; all functional memory accesses should use
149 // one of the FunctionalMemory pointers above.
155 * Temporary storage to pass the source address from copy_load to
157 * @todo Remove this temporary when we have a better way to do it.
161 * Temp storage for the physical source address of a copy.
162 * @todo Remove this temporary when we have a better way to do it.
164 Addr copySrcPhysAddr;
168 * number of executed instructions, for matching with syscall trace
169 * points in EIO files.
171 Counter func_exe_inst;
174 // Count failed store conditionals so we can warn of apparent
175 // application deadlock situations.
176 unsigned storeCondFailures;
178 // constructor: initialize context from given process structure
180 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
181 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
183 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
184 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
187 virtual ~ExecContext();
189 virtual void takeOverFrom(ExecContext *oldContext);
191 void regStats(const std::string &name);
193 void serialize(std::ostream &os);
194 void unserialize(Checkpoint *cp, const std::string §ion);
197 bool validInstAddr(Addr addr) { return true; }
198 bool validDataAddr(Addr addr) { return true; }
199 int getInstAsid() { return regs.instAsid(); }
200 int getDataAsid() { return regs.dataAsid(); }
202 Fault translateInstReq(MemReqPtr &req)
204 return itb->translate(req);
207 Fault translateDataReadReq(MemReqPtr &req)
209 return dtb->translate(req, false);
212 Fault translateDataWriteReq(MemReqPtr &req)
214 return dtb->translate(req, true);
218 bool validInstAddr(Addr addr)
219 { return process->validInstAddr(addr); }
221 bool validDataAddr(Addr addr)
222 { return process->validDataAddr(addr); }
224 int getInstAsid() { return asid; }
225 int getDataAsid() { return asid; }
227 Fault dummyTranslation(MemReqPtr &req)
230 assert((req->vaddr >> 48 & 0xffff) == 0);
233 // put the asid in the upper 16 bits of the paddr
234 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
235 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
238 Fault translateInstReq(MemReqPtr &req)
240 return dummyTranslation(req);
242 Fault translateDataReadReq(MemReqPtr &req)
244 return dummyTranslation(req);
246 Fault translateDataWriteReq(MemReqPtr &req)
248 return dummyTranslation(req);
254 Fault read(MemReqPtr &req, T &data)
256 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
257 if (req->flags & LOCKED) {
258 MiscRegFile *cregs = &req->xc->regs.miscRegs;
259 cregs->lock_addr = req->paddr;
260 cregs->lock_flag = true;
265 error = mem->read(req, data);
271 Fault write(MemReqPtr &req, T &data)
273 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
277 // If this is a store conditional, act appropriately
278 if (req->flags & LOCKED) {
279 cregs = &req->xc->regs.miscRegs;
281 if (req->flags & UNCACHEABLE) {
282 // Don't update result register (see stq_c in isa_desc)
284 req->xc->storeCondFailures = 0;//Needed? [RGD]
286 req->result = cregs->lock_flag;
287 if (!cregs->lock_flag ||
288 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
289 cregs->lock_flag = false;
290 if (((++req->xc->storeCondFailures) % 100000) == 0) {
291 std::cerr << "Warning: "
292 << req->xc->storeCondFailures
293 << " consecutive store conditional failures "
294 << "on cpu " << req->xc->cpu_id
299 else req->xc->storeCondFailures = 0;
303 // Need to clear any locked flags on other proccessors for
304 // this address. Only do this for succsful Store Conditionals
305 // and all other stores (WH64?). Unsuccessful Store
306 // Conditionals would have returned above, and wouldn't fall
308 for (int i = 0; i < system->execContexts.size(); i++){
309 cregs = &system->execContexts[i]->regs.miscRegs;
310 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
311 cregs->lock_flag = false;
316 return mem->write(req, (T)htoa(data));
319 virtual bool misspeculating();
322 MachInst getInst() { return inst; }
324 void setInst(MachInst new_inst)
329 Fault instRead(MemReqPtr &req)
331 return mem->read(req, inst);
335 // New accessors for new decoder.
337 uint64_t readIntReg(int reg_idx)
339 return regs.intRegFile[reg_idx];
342 float readFloatRegSingle(int reg_idx)
344 return (float)regs.floatRegFile.d[reg_idx];
347 double readFloatRegDouble(int reg_idx)
349 return regs.floatRegFile.d[reg_idx];
352 uint64_t readFloatRegInt(int reg_idx)
354 return regs.floatRegFile.q[reg_idx];
357 void setIntReg(int reg_idx, uint64_t val)
359 regs.intRegFile[reg_idx] = val;
362 void setFloatRegSingle(int reg_idx, float val)
364 regs.floatRegFile.d[reg_idx] = (double)val;
367 void setFloatRegDouble(int reg_idx, double val)
369 regs.floatRegFile.d[reg_idx] = val;
372 void setFloatRegInt(int reg_idx, uint64_t val)
374 regs.floatRegFile.q[reg_idx] = val;
382 void setNextPC(uint64_t val)
389 return regs.miscRegs.uniq;
392 void setUniq(uint64_t val)
394 regs.miscRegs.uniq = val;
399 return regs.miscRegs.fpcr;
402 void setFpcr(uint64_t val)
404 regs.miscRegs.fpcr = val;
408 uint64_t readIpr(int idx, Fault &fault);
409 Fault setIpr(int idx, uint64_t val);
410 int readIntrFlag() { return regs.intrflag; }
411 void setIntrFlag(int val) { regs.intrflag = val; }
413 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
414 void ev5_trap(Fault fault);
415 bool simPalCheck(int palFunc);
418 /** Meant to be more generic trap function to be
419 * called when an instruction faults.
420 * @param fault The fault generated by executing the instruction.
421 * @todo How to do this properly so it's dependent upon ISA only?
424 void trap(Fault fault);
427 IntReg getSyscallArg(int i)
429 return regs.intRegFile[ArgumentReg0 + i];
432 // used to shift args for indirect syscall
433 void setSyscallArg(int i, IntReg val)
435 regs.intRegFile[ArgumentReg0 + i] = val;
438 void setSyscallReturn(int64_t return_value)
440 // check for error condition. Alpha syscall convention is to
441 // indicate success/failure in reg a3 (r19) and put the
442 // return value itself in the standard return value reg (v0).
443 const int RegA3 = 19; // only place this is used
444 if (return_value >= 0) {
446 regs.intRegFile[RegA3] = 0;
447 regs.intRegFile[ReturnValueReg] = return_value;
449 // got an error, return details
450 regs.intRegFile[RegA3] = (IntReg) -1;
451 regs.intRegFile[ReturnValueReg] = -return_value;
457 process->syscall(this);
463 // for non-speculative execution context, spec_mode is always false
465 ExecContext::misspeculating()
470 #endif // __EXEC_CONTEXT_HH__