cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2001-2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __EXEC_CONTEXT_HH__
  30 #define __EXEC_CONTEXT_HH__
  31
  32 #include "sim/host.hh"
  33 #include "mem/mem_req.hh"
  34 #include "mem/functional_mem/functional_memory.hh"
  35 #include "sim/serialize.hh"
  36 #include "targetarch/byte_swap.hh"
  37
  38 // forward declaration: see functional_memory.hh
  39 class FunctionalMemory;
  40 class PhysicalMemory;
  41 class BaseCPU;
  42
  43 #ifdef FULL_SYSTEM
  44
  45 #include "sim/system.hh"
  46 #include "targetarch/alpha_memory.hh"
  47
  48 class MemoryController;
  49 class StaticInstBase;
  50 namespace Kernel { class Binning; class Statistics; }
  51
  52 #else // !FULL_SYSTEM
  53
  54 #include "sim/process.hh"
  55
  56 #endif // FULL_SYSTEM
  57
  58 //
  59 // The ExecContext object represents a functional context for
  60 // instruction execution.  It incorporates everything required for
  61 // architecture-level functional simulation of a single thread.
  62 //
  63
  64 class ExecContext
  65 {
  66   public:
  67     enum Status
  68     {
  69         /// Initialized but not running yet.  All CPUs start in
  70         /// this state, but most transition to Active on cycle 1.
  71         /// In MP or SMT systems, non-primary contexts will stay
  72         /// in this state until a thread is assigned to them.
  73         Unallocated,
  74
  75         /// Running.  Instructions should be executed only when
  76         /// the context is in this state.
  77         Active,
  78
  79         /// Temporarily inactive.  Entered while waiting for
  80         /// synchronization, etc.
  81         Suspended,
  82
  83         /// Permanently shut down.  Entered when target executes
  84         /// m5exit pseudo-instruction.  When all contexts enter
  85         /// this state, the simulation will terminate.
  86         Halted
  87     };
  88
  89   private:
  90     Status _status;
  91
  92   public:
  93     Status status() const { return _status; }
  94
  95     /// Set the status to Active.  Optional delay indicates number of
  96     /// cycles to wait before beginning execution.
  97     void activate(int delay = 1);
  98
  99     /// Set the status to Suspended.
 100     void suspend();
 101
 102     /// Set the status to Unallocated.
 103     void deallocate();
 104
 105     /// Set the status to Halted.
 106     void halt();
 107
 108   public:
 109     RegFile regs;       // correct-path register context
 110
 111     // pointer to CPU associated with this context
 112     BaseCPU *cpu;
 113
 114     // Current instruction
 115     MachInst inst;
 116
 117     // Index of hardware thread context on the CPU that this represents.
 118     int thread_num;
 119
 120     // ID of this context w.r.t. the System or Process object to which
 121     // it belongs.  For full-system mode, this is the system CPU ID.
 122     int cpu_id;
 123
 124 #ifdef FULL_SYSTEM
 125     FunctionalMemory *mem;
 126     AlphaITB *itb;
 127     AlphaDTB *dtb;
 128     System *system;
 129
 130     // the following two fields are redundant, since we can always
 131     // look them up through the system pointer, but we'll leave them
 132     // here for now for convenience
 133     MemoryController *memctrl;
 134     PhysicalMemory *physmem;
 135
 136     Kernel::Binning *kernelBinning;
 137     Kernel::Statistics *kernelStats;
 138     bool bin;
 139     bool fnbin;
 140     void execute(const StaticInstBase *inst);
 141
 142 #else
 143     Process *process;
 144
 145     FunctionalMemory *mem;      // functional storage for process address space
 146
 147     // Address space ID.  Note that this is used for TIMING cache
 148     // simulation only; all functional memory accesses should use
 149     // one of the FunctionalMemory pointers above.
 150     short asid;
 151
 152 #endif
 153
 154     /**
 155      * Temporary storage to pass the source address from copy_load to
 156      * copy_store.
 157      * @todo Remove this temporary when we have a better way to do it.
 158      */
 159     Addr copySrcAddr;
 160     /**
 161      * Temp storage for the physical source address of a copy.
 162      * @todo Remove this temporary when we have a better way to do it.
 163      */
 164     Addr copySrcPhysAddr;
 165
 166
 167     /*
 168      * number of executed instructions, for matching with syscall trace
 169      * points in EIO files.
 170      */
 171     Counter func_exe_inst;
 172
 173     //
 174     // Count failed store conditionals so we can warn of apparent
 175     // application deadlock situations.
 176     unsigned storeCondFailures;
 177
 178     // constructor: initialize context from given process structure
 179 #ifdef FULL_SYSTEM
 180     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 181                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 182 #else
 183     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 184     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 185                 int _asid);
 186 #endif
 187     virtual ~ExecContext();
 188
 189     virtual void takeOverFrom(ExecContext *oldContext);
 190
 191     void regStats(const std::string &name);
 192
 193     void serialize(std::ostream &os);
 194     void unserialize(Checkpoint *cp, const std::string &section);
 195
 196 #ifdef FULL_SYSTEM
 197     bool validInstAddr(Addr addr) { return true; }
 198     bool validDataAddr(Addr addr) { return true; }
 199     int getInstAsid() { return regs.instAsid(); }
 200     int getDataAsid() { return regs.dataAsid(); }
 201
 202     Fault translateInstReq(MemReqPtr &req)
 203     {
 204         return itb->translate(req);
 205     }
 206
 207     Fault translateDataReadReq(MemReqPtr &req)
 208     {
 209         return dtb->translate(req, false);
 210     }
 211
 212     Fault translateDataWriteReq(MemReqPtr &req)
 213     {
 214         return dtb->translate(req, true);
 215     }
 216
 217 #else
 218     bool validInstAddr(Addr addr)
 219     { return process->validInstAddr(addr); }
 220
 221     bool validDataAddr(Addr addr)
 222     { return process->validDataAddr(addr); }
 223
 224     int getInstAsid() { return asid; }
 225     int getDataAsid() { return asid; }
 226
 227     Fault dummyTranslation(MemReqPtr &req)
 228     {
 229 #if 0
 230         assert((req->vaddr >> 48 & 0xffff) == 0);
 231 #endif
 232
 233         // put the asid in the upper 16 bits of the paddr
 234         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 235         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 236         return No_Fault;
 237     }
 238     Fault translateInstReq(MemReqPtr &req)
 239     {
 240         return dummyTranslation(req);
 241     }
 242     Fault translateDataReadReq(MemReqPtr &req)
 243     {
 244         return dummyTranslation(req);
 245     }
 246     Fault translateDataWriteReq(MemReqPtr &req)
 247     {
 248         return dummyTranslation(req);
 249     }
 250
 251 #endif
 252
 253     template <class T>
 254     Fault read(MemReqPtr &req, T &data)
 255     {
 256 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 257         if (req->flags & LOCKED) {
 258             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 259             cregs->lock_addr = req->paddr;
 260             cregs->lock_flag = true;
 261         }
 262 #endif
 263
 264         Fault error;
 265         error = mem->read(req, data);
 266         data = htoa(data);
 267         return error;
 268     }
 269
 270     template <class T>
 271     Fault write(MemReqPtr &req, T &data)
 272     {
 273 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 274
 275         MiscRegFile *cregs;
 276
 277         // If this is a store conditional, act appropriately
 278         if (req->flags & LOCKED) {
 279             cregs = &req->xc->regs.miscRegs;
 280
 281             if (req->flags & UNCACHEABLE) {
 282                 // Don't update result register (see stq_c in isa_desc)
 283                 req->result = 2;
 284                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 285             } else {
 286                 req->result = cregs->lock_flag;
 287                 if (!cregs->lock_flag ||
 288                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 289                     cregs->lock_flag = false;
 290                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 291                         std::cerr << "Warning: "
 292                                   << req->xc->storeCondFailures
 293                                   << " consecutive store conditional failures "
 294                                   << "on cpu " << req->xc->cpu_id
 295                                   << std::endl;
 296                     }
 297                     return No_Fault;
 298                 }
 299                 else req->xc->storeCondFailures = 0;
 300             }
 301         }
 302
 303         // Need to clear any locked flags on other proccessors for
 304         // this address.  Only do this for succsful Store Conditionals
 305         // and all other stores (WH64?).  Unsuccessful Store
 306         // Conditionals would have returned above, and wouldn't fall
 307         // through.
 308         for (int i = 0; i < system->execContexts.size(); i++){
 309             cregs = &system->execContexts[i]->regs.miscRegs;
 310             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 311                 cregs->lock_flag = false;
 312             }
 313         }
 314
 315 #endif
 316         return mem->write(req, (T)htoa(data));
 317     }
 318
 319     virtual bool misspeculating();
 320
 321
 322     MachInst getInst() { return inst; }
 323
 324     void setInst(MachInst new_inst)
 325     {
 326         inst = new_inst;
 327     }
 328
 329     Fault instRead(MemReqPtr &req)
 330     {
 331         return mem->read(req, inst);
 332     }
 333
 334     //
 335     // New accessors for new decoder.
 336     //
 337     uint64_t readIntReg(int reg_idx)
 338     {
 339         return regs.intRegFile[reg_idx];
 340     }
 341
 342     float readFloatRegSingle(int reg_idx)
 343     {
 344         return (float)regs.floatRegFile.d[reg_idx];
 345     }
 346
 347     double readFloatRegDouble(int reg_idx)
 348     {
 349         return regs.floatRegFile.d[reg_idx];
 350     }
 351
 352     uint64_t readFloatRegInt(int reg_idx)
 353     {
 354         return regs.floatRegFile.q[reg_idx];
 355     }
 356
 357     void setIntReg(int reg_idx, uint64_t val)
 358     {
 359         regs.intRegFile[reg_idx] = val;
 360     }
 361
 362     void setFloatRegSingle(int reg_idx, float val)
 363     {
 364         regs.floatRegFile.d[reg_idx] = (double)val;
 365     }
 366
 367     void setFloatRegDouble(int reg_idx, double val)
 368     {
 369         regs.floatRegFile.d[reg_idx] = val;
 370     }
 371
 372     void setFloatRegInt(int reg_idx, uint64_t val)
 373     {
 374         regs.floatRegFile.q[reg_idx] = val;
 375     }
 376
 377     uint64_t readPC()
 378     {
 379         return regs.pc;
 380     }
 381
 382     void setNextPC(uint64_t val)
 383     {
 384         regs.npc = val;
 385     }
 386
 387     uint64_t readUniq()
 388     {
 389         return regs.miscRegs.uniq;
 390     }
 391
 392     void setUniq(uint64_t val)
 393     {
 394         regs.miscRegs.uniq = val;
 395     }
 396
 397     uint64_t readFpcr()
 398     {
 399         return regs.miscRegs.fpcr;
 400     }
 401
 402     void setFpcr(uint64_t val)
 403     {
 404         regs.miscRegs.fpcr = val;
 405     }
 406
 407 #ifdef FULL_SYSTEM
 408     uint64_t readIpr(int idx, Fault &fault);
 409     Fault setIpr(int idx, uint64_t val);
 410     int readIntrFlag() { return regs.intrflag; }
 411     void setIntrFlag(int val) { regs.intrflag = val; }
 412     Fault hwrei();
 413     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
 414     void ev5_trap(Fault fault);
 415     bool simPalCheck(int palFunc);
 416 #endif
 417
 418     /** Meant to be more generic trap function to be
 419      *  called when an instruction faults.
 420      *  @param fault The fault generated by executing the instruction.
 421      *  @todo How to do this properly so it's dependent upon ISA only?
 422      */
 423
 424     void trap(Fault fault);
 425
 426 #ifndef FULL_SYSTEM
 427     IntReg getSyscallArg(int i)
 428     {
 429         return regs.intRegFile[ArgumentReg0 + i];
 430     }
 431
 432     // used to shift args for indirect syscall
 433     void setSyscallArg(int i, IntReg val)
 434     {
 435         regs.intRegFile[ArgumentReg0 + i] = val;
 436     }
 437
 438     void setSyscallReturn(int64_t return_value)
 439     {
 440         // check for error condition.  Alpha syscall convention is to
 441         // indicate success/failure in reg a3 (r19) and put the
 442         // return value itself in the standard return value reg (v0).
 443         const int RegA3 = 19;   // only place this is used
 444         if (return_value >= 0) {
 445             // no error
 446             regs.intRegFile[RegA3] = 0;
 447             regs.intRegFile[ReturnValueReg] = return_value;
 448         } else {
 449             // got an error, return details
 450             regs.intRegFile[RegA3] = (IntReg) -1;
 451             regs.intRegFile[ReturnValueReg] = -return_value;
 452         }
 453     }
 454
 455     void syscall()
 456     {
 457         process->syscall(this);
 458     }
 459 #endif
 460 };
 461
 462
 463 // for non-speculative execution context, spec_mode is always false
 464 inline bool
 465 ExecContext::misspeculating()
 466 {
 467     return false;
 468 }
 469
 470 #endif // __EXEC_CONTEXT_HH__