cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __EXEC_CONTEXT_HH__
  30 #define __EXEC_CONTEXT_HH__
  31
  32 #include "sim/host.hh"
  33 #include "mem/mem_req.hh"
  34 #include "sim/serialize.hh"
  35
  36 // forward declaration: see functional_memory.hh
  37 class FunctionalMemory;
  38 class PhysicalMemory;
  39 class BaseCPU;
  40
  41 #ifdef FULL_SYSTEM
  42
  43 #include "targetarch/alpha_memory.hh"
  44 class MemoryController;
  45
  46 #include "kern/tru64/kernel_stats.hh"
  47 #include "sim/system.hh"
  48 #include "sim/sw_context.hh"
  49
  50 #else // !FULL_SYSTEM
  51
  52 #include "sim/process.hh"
  53
  54 #endif // FULL_SYSTEM
  55
  56 //
  57 // The ExecContext object represents a functional context for
  58 // instruction execution.  It incorporates everything required for
  59 // architecture-level functional simulation of a single thread.
  60 //
  61
  62 class ExecContext
  63 {
  64   public:
  65     enum Status
  66     {
  67         /// Initialized but not running yet.  All CPUs start in
  68         /// this state, but most transition to Active on cycle 1.
  69         /// In MP or SMT systems, non-primary contexts will stay
  70         /// in this state until a thread is assigned to them.
  71         Unallocated,
  72
  73         /// Running.  Instructions should be executed only when
  74         /// the context is in this state.
  75         Active,
  76
  77         /// Temporarily inactive.  Entered while waiting for
  78         /// synchronization, etc.
  79         Suspended,
  80
  81         /// Permanently shut down.  Entered when target executes
  82         /// m5exit pseudo-instruction.  When all contexts enter
  83         /// this state, the simulation will terminate.
  84         Halted
  85     };
  86
  87   private:
  88     Status _status;
  89
  90   public:
  91     Status status() const { return _status; }
  92
  93     /// Set the status to Active.  Optional delay indicates number of
  94     /// cycles to wait before beginning execution.
  95     void activate(int delay = 1);
  96
  97     /// Set the status to Suspended.
  98     void suspend();
  99
 100     /// Set the status to Unallocated.
 101     void deallocate();
 102
 103     /// Set the status to Halted.
 104     void halt();
 105
 106 #ifdef FULL_SYSTEM
 107   public:
 108     KernelStats kernelStats;
 109 #endif
 110
 111   public:
 112     RegFile regs;       // correct-path register context
 113
 114     // pointer to CPU associated with this context
 115     BaseCPU *cpu;
 116
 117     // Index of hardware thread context on the CPU that this represents.
 118     int thread_num;
 119
 120     // ID of this context w.r.t. the System or Process object to which
 121     // it belongs.  For full-system mode, this is the system CPU ID.
 122     int cpu_id;
 123
 124 #ifdef FULL_SYSTEM
 125
 126     FunctionalMemory *mem;
 127     AlphaItb *itb;
 128     AlphaDtb *dtb;
 129     System *system;
 130
 131     // the following two fields are redundant, since we can always
 132     // look them up through the system pointer, but we'll leave them
 133     // here for now for convenience
 134     MemoryController *memCtrl;
 135     PhysicalMemory *physmem;
 136
 137     SWContext *swCtx;
 138 #else
 139     Process *process;
 140
 141     FunctionalMemory *mem;      // functional storage for process address space
 142
 143     // Address space ID.  Note that this is used for TIMING cache
 144     // simulation only; all functional memory accesses should use
 145     // one of the FunctionalMemory pointers above.
 146     short asid;
 147
 148 #endif
 149
 150
 151     /*
 152      * number of executed instructions, for matching with syscall trace
 153      * points in EIO files.
 154      */
 155     Counter func_exe_inst;
 156
 157     //
 158     // Count failed store conditionals so we can warn of apparent
 159     // application deadlock situations.
 160     unsigned storeCondFailures;
 161
 162     // constructor: initialize context from given process structure
 163 #ifdef FULL_SYSTEM
 164     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 165                 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
 166 #else
 167     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 168     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 169                 int _asid);
 170 #endif
 171     virtual ~ExecContext() {}
 172
 173     virtual void takeOverFrom(ExecContext *oldContext);
 174
 175     void regStats(const std::string &name);
 176
 177     void serialize(std::ostream &os);
 178     void unserialize(Checkpoint *cp, const std::string &section);
 179
 180 #ifdef FULL_SYSTEM
 181     bool validInstAddr(Addr addr) { return true; }
 182     bool validDataAddr(Addr addr) { return true; }
 183     int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
 184     int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
 185
 186     Fault translateInstReq(MemReqPtr &req)
 187     {
 188         return itb->translate(req);
 189     }
 190
 191     Fault translateDataReadReq(MemReqPtr &req)
 192     {
 193         return dtb->translate(req, false);
 194     }
 195
 196     Fault translateDataWriteReq(MemReqPtr &req)
 197     {
 198         return dtb->translate(req, true);
 199     }
 200
 201 #else
 202     bool validInstAddr(Addr addr)
 203     { return process->validInstAddr(addr); }
 204
 205     bool validDataAddr(Addr addr)
 206     { return process->validDataAddr(addr); }
 207
 208     int getInstAsid() { return asid; }
 209     int getDataAsid() { return asid; }
 210
 211     Fault dummyTranslation(MemReqPtr &req)
 212     {
 213 #if 0
 214         assert((req->vaddr >> 48 & 0xffff) == 0);
 215 #endif
 216
 217         // put the asid in the upper 16 bits of the paddr
 218         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 219         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 220         return No_Fault;
 221     }
 222     Fault translateInstReq(MemReqPtr &req)
 223     {
 224         return dummyTranslation(req);
 225     }
 226     Fault translateDataReadReq(MemReqPtr &req)
 227     {
 228         return dummyTranslation(req);
 229     }
 230     Fault translateDataWriteReq(MemReqPtr &req)
 231     {
 232         return dummyTranslation(req);
 233     }
 234
 235 #endif
 236
 237     template <class T>
 238     Fault read(MemReqPtr &req, T &data)
 239     {
 240 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 241         if (req->flags & LOCKED) {
 242             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 243             cregs->lock_addr = req->paddr;
 244             cregs->lock_flag = true;
 245         }
 246 #endif
 247         return mem->read(req, data);
 248     }
 249
 250     template <class T>
 251     Fault write(MemReqPtr &req, T &data)
 252     {
 253 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 254
 255         MiscRegFile *cregs;
 256
 257         // If this is a store conditional, act appropriately
 258         if (req->flags & LOCKED) {
 259             cregs = &req->xc->regs.miscRegs;
 260
 261             if (req->flags & UNCACHEABLE) {
 262                 // Don't update result register (see stq_c in isa_desc)
 263                 req->result = 2;
 264                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 265             } else {
 266                 req->result = cregs->lock_flag;
 267                 if (!cregs->lock_flag ||
 268                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 269                     cregs->lock_flag = false;
 270                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 271                         std::cerr << "Warning: "
 272                                   << req->xc->storeCondFailures
 273                                   << " consecutive store conditional failures "
 274                                   << "on cpu " << req->xc->cpu_id
 275                                   << std::endl;
 276                     }
 277                     return No_Fault;
 278                 }
 279                 else req->xc->storeCondFailures = 0;
 280             }
 281         }
 282
 283         // Need to clear any locked flags on other proccessors for
 284         // this address.  Only do this for succsful Store Conditionals
 285         // and all other stores (WH64?).  Unsuccessful Store
 286         // Conditionals would have returned above, and wouldn't fall
 287         // through.
 288         for (int i = 0; i < system->execContexts.size(); i++){
 289             cregs = &system->execContexts[i]->regs.miscRegs;
 290             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 291                 cregs->lock_flag = false;
 292             }
 293         }
 294
 295 #endif
 296         return mem->write(req, data);
 297     }
 298
 299     virtual bool misspeculating();
 300
 301
 302     //
 303     // New accessors for new decoder.
 304     //
 305     uint64_t readIntReg(int reg_idx)
 306     {
 307         return regs.intRegFile[reg_idx];
 308     }
 309
 310     float readFloatRegSingle(int reg_idx)
 311     {
 312         return (float)regs.floatRegFile.d[reg_idx];
 313     }
 314
 315     double readFloatRegDouble(int reg_idx)
 316     {
 317         return regs.floatRegFile.d[reg_idx];
 318     }
 319
 320     uint64_t readFloatRegInt(int reg_idx)
 321     {
 322         return regs.floatRegFile.q[reg_idx];
 323     }
 324
 325     void setIntReg(int reg_idx, uint64_t val)
 326     {
 327         regs.intRegFile[reg_idx] = val;
 328     }
 329
 330     void setFloatRegSingle(int reg_idx, float val)
 331     {
 332         regs.floatRegFile.d[reg_idx] = (double)val;
 333     }
 334
 335     void setFloatRegDouble(int reg_idx, double val)
 336     {
 337         regs.floatRegFile.d[reg_idx] = val;
 338     }
 339
 340     void setFloatRegInt(int reg_idx, uint64_t val)
 341     {
 342         regs.floatRegFile.q[reg_idx] = val;
 343     }
 344
 345     uint64_t readPC()
 346     {
 347         return regs.pc;
 348     }
 349
 350     void setNextPC(uint64_t val)
 351     {
 352         regs.npc = val;
 353     }
 354
 355     uint64_t readUniq()
 356     {
 357         return regs.miscRegs.uniq;
 358     }
 359
 360     void setUniq(uint64_t val)
 361     {
 362         regs.miscRegs.uniq = val;
 363     }
 364
 365     uint64_t readFpcr()
 366     {
 367         return regs.miscRegs.fpcr;
 368     }
 369
 370     void setFpcr(uint64_t val)
 371     {
 372         regs.miscRegs.fpcr = val;
 373     }
 374
 375 #ifdef FULL_SYSTEM
 376     uint64_t readIpr(int idx, Fault &fault);
 377     Fault setIpr(int idx, uint64_t val);
 378     Fault hwrei();
 379     void ev5_trap(Fault fault);
 380     bool simPalCheck(int palFunc);
 381 #endif
 382
 383 #ifndef FULL_SYSTEM
 384     IntReg getSyscallArg(int i)
 385     {
 386         return regs.intRegFile[ArgumentReg0 + i];
 387     }
 388
 389     // used to shift args for indirect syscall
 390     void setSyscallArg(int i, IntReg val)
 391     {
 392         regs.intRegFile[ArgumentReg0 + i] = val;
 393     }
 394
 395     void setSyscallReturn(int64_t return_value)
 396     {
 397         // check for error condition.  Alpha syscall convention is to
 398         // indicate success/failure in reg a3 (r19) and put the
 399         // return value itself in the standard return value reg (v0).
 400         const int RegA3 = 19;   // only place this is used
 401         if (return_value >= 0) {
 402             // no error
 403             regs.intRegFile[RegA3] = 0;
 404             regs.intRegFile[ReturnValueReg] = return_value;
 405         } else {
 406             // got an error, return details
 407             regs.intRegFile[RegA3] = (IntReg) -1;
 408             regs.intRegFile[ReturnValueReg] = -return_value;
 409         }
 410     }
 411
 412     void syscall()
 413     {
 414         process->syscall(this);
 415     }
 416 #endif
 417 };
 418
 419
 420 // for non-speculative execution context, spec_mode is always false
 421 inline bool
 422 ExecContext::misspeculating()
 423 {
 424     return false;
 425 }
 426
 427 #endif // __EXEC_CONTEXT_HH__