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29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "mem/mem_req.hh"
34 #include "sim/serialize.hh"
36 // forward declaration: see functional_memory.hh
37 class FunctionalMemory;
43 #include "targetarch/alpha_memory.hh"
44 class MemoryController;
46 #include "kern/tru64/kernel_stats.hh"
47 #include "sim/system.hh"
48 #include "sim/sw_context.hh"
52 #include "sim/process.hh"
57 // The ExecContext object represents a functional context for
58 // instruction execution. It incorporates everything required for
59 // architecture-level functional simulation of a single thread.
67 /// Initialized but not running yet. All CPUs start in
68 /// this state, but most transition to Active on cycle 1.
69 /// In MP or SMT systems, non-primary contexts will stay
70 /// in this state until a thread is assigned to them.
73 /// Running. Instructions should be executed only when
74 /// the context is in this state.
77 /// Temporarily inactive. Entered while waiting for
78 /// synchronization, etc.
81 /// Permanently shut down. Entered when target executes
82 /// m5exit pseudo-instruction. When all contexts enter
83 /// this state, the simulation will terminate.
91 Status status() const { return _status; }
93 /// Set the status to Active. Optional delay indicates number of
94 /// cycles to wait before beginning execution.
95 void activate(int delay = 1);
97 /// Set the status to Suspended.
100 /// Set the status to Unallocated.
103 /// Set the status to Halted.
108 KernelStats kernelStats;
112 RegFile regs; // correct-path register context
114 // pointer to CPU associated with this context
117 // Index of hardware thread context on the CPU that this represents.
120 // ID of this context w.r.t. the System or Process object to which
121 // it belongs. For full-system mode, this is the system CPU ID.
126 FunctionalMemory *mem;
131 // the following two fields are redundant, since we can always
132 // look them up through the system pointer, but we'll leave them
133 // here for now for convenience
134 MemoryController *memCtrl;
135 PhysicalMemory *physmem;
141 FunctionalMemory *mem; // functional storage for process address space
143 // Address space ID. Note that this is used for TIMING cache
144 // simulation only; all functional memory accesses should use
145 // one of the FunctionalMemory pointers above.
152 * number of executed instructions, for matching with syscall trace
153 * points in EIO files.
155 Counter func_exe_inst;
158 // Count failed store conditionals so we can warn of apparent
159 // application deadlock situations.
160 unsigned storeCondFailures;
162 // constructor: initialize context from given process structure
164 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
165 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
167 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
168 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
171 virtual ~ExecContext() {}
173 virtual void takeOverFrom(ExecContext *oldContext);
175 void regStats(const std::string &name);
177 void serialize(std::ostream &os);
178 void unserialize(Checkpoint *cp, const std::string §ion);
181 bool validInstAddr(Addr addr) { return true; }
182 bool validDataAddr(Addr addr) { return true; }
183 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
184 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
186 Fault translateInstReq(MemReqPtr &req)
188 return itb->translate(req);
191 Fault translateDataReadReq(MemReqPtr &req)
193 return dtb->translate(req, false);
196 Fault translateDataWriteReq(MemReqPtr &req)
198 return dtb->translate(req, true);
202 bool validInstAddr(Addr addr)
203 { return process->validInstAddr(addr); }
205 bool validDataAddr(Addr addr)
206 { return process->validDataAddr(addr); }
208 int getInstAsid() { return asid; }
209 int getDataAsid() { return asid; }
211 Fault dummyTranslation(MemReqPtr &req)
214 assert((req->vaddr >> 48 & 0xffff) == 0);
217 // put the asid in the upper 16 bits of the paddr
218 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
219 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
222 Fault translateInstReq(MemReqPtr &req)
224 return dummyTranslation(req);
226 Fault translateDataReadReq(MemReqPtr &req)
228 return dummyTranslation(req);
230 Fault translateDataWriteReq(MemReqPtr &req)
232 return dummyTranslation(req);
238 Fault read(MemReqPtr &req, T &data)
240 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
241 if (req->flags & LOCKED) {
242 MiscRegFile *cregs = &req->xc->regs.miscRegs;
243 cregs->lock_addr = req->paddr;
244 cregs->lock_flag = true;
247 return mem->read(req, data);
251 Fault write(MemReqPtr &req, T &data)
253 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
257 // If this is a store conditional, act appropriately
258 if (req->flags & LOCKED) {
259 cregs = &req->xc->regs.miscRegs;
261 if (req->flags & UNCACHEABLE) {
262 // Don't update result register (see stq_c in isa_desc)
264 req->xc->storeCondFailures = 0;//Needed? [RGD]
266 req->result = cregs->lock_flag;
267 if (!cregs->lock_flag ||
268 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
269 cregs->lock_flag = false;
270 if (((++req->xc->storeCondFailures) % 100000) == 0) {
271 std::cerr << "Warning: "
272 << req->xc->storeCondFailures
273 << " consecutive store conditional failures "
274 << "on cpu " << req->xc->cpu_id
279 else req->xc->storeCondFailures = 0;
283 // Need to clear any locked flags on other proccessors for
284 // this address. Only do this for succsful Store Conditionals
285 // and all other stores (WH64?). Unsuccessful Store
286 // Conditionals would have returned above, and wouldn't fall
288 for (int i = 0; i < system->execContexts.size(); i++){
289 cregs = &system->execContexts[i]->regs.miscRegs;
290 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
291 cregs->lock_flag = false;
296 return mem->write(req, data);
299 virtual bool misspeculating();
303 // New accessors for new decoder.
305 uint64_t readIntReg(int reg_idx)
307 return regs.intRegFile[reg_idx];
310 float readFloatRegSingle(int reg_idx)
312 return (float)regs.floatRegFile.d[reg_idx];
315 double readFloatRegDouble(int reg_idx)
317 return regs.floatRegFile.d[reg_idx];
320 uint64_t readFloatRegInt(int reg_idx)
322 return regs.floatRegFile.q[reg_idx];
325 void setIntReg(int reg_idx, uint64_t val)
327 regs.intRegFile[reg_idx] = val;
330 void setFloatRegSingle(int reg_idx, float val)
332 regs.floatRegFile.d[reg_idx] = (double)val;
335 void setFloatRegDouble(int reg_idx, double val)
337 regs.floatRegFile.d[reg_idx] = val;
340 void setFloatRegInt(int reg_idx, uint64_t val)
342 regs.floatRegFile.q[reg_idx] = val;
350 void setNextPC(uint64_t val)
357 return regs.miscRegs.uniq;
360 void setUniq(uint64_t val)
362 regs.miscRegs.uniq = val;
367 return regs.miscRegs.fpcr;
370 void setFpcr(uint64_t val)
372 regs.miscRegs.fpcr = val;
376 uint64_t readIpr(int idx, Fault &fault);
377 Fault setIpr(int idx, uint64_t val);
379 void ev5_trap(Fault fault);
380 bool simPalCheck(int palFunc);
384 IntReg getSyscallArg(int i)
386 return regs.intRegFile[ArgumentReg0 + i];
389 // used to shift args for indirect syscall
390 void setSyscallArg(int i, IntReg val)
392 regs.intRegFile[ArgumentReg0 + i] = val;
395 void setSyscallReturn(int64_t return_value)
397 // check for error condition. Alpha syscall convention is to
398 // indicate success/failure in reg a3 (r19) and put the
399 // return value itself in the standard return value reg (v0).
400 const int RegA3 = 19; // only place this is used
401 if (return_value >= 0) {
403 regs.intRegFile[RegA3] = 0;
404 regs.intRegFile[ReturnValueReg] = return_value;
406 // got an error, return details
407 regs.intRegFile[RegA3] = (IntReg) -1;
408 regs.intRegFile[ReturnValueReg] = -return_value;
414 process->syscall(this);
420 // for non-speculative execution context, spec_mode is always false
422 ExecContext::misspeculating()
427 #endif // __EXEC_CONTEXT_HH__