2 * Copyright (c) 2001-2004 The Regents of The University of Michigan
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29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "mem/mem_req.hh"
34 #include "mem/functional_mem/functional_memory.hh"
35 #include "sim/serialize.hh"
36 #include "targetarch/byte_swap.hh"
38 // forward declaration: see functional_memory.hh
39 class FunctionalMemory;
45 #include "targetarch/alpha_memory.hh"
46 class MemoryController;
48 #include "kern/kernel_stats.hh"
49 #include "sim/system.hh"
50 #include "sim/sw_context.hh"
54 #include "sim/process.hh"
59 // The ExecContext object represents a functional context for
60 // instruction execution. It incorporates everything required for
61 // architecture-level functional simulation of a single thread.
69 /// Initialized but not running yet. All CPUs start in
70 /// this state, but most transition to Active on cycle 1.
71 /// In MP or SMT systems, non-primary contexts will stay
72 /// in this state until a thread is assigned to them.
75 /// Running. Instructions should be executed only when
76 /// the context is in this state.
79 /// Temporarily inactive. Entered while waiting for
80 /// synchronization, etc.
83 /// Permanently shut down. Entered when target executes
84 /// m5exit pseudo-instruction. When all contexts enter
85 /// this state, the simulation will terminate.
93 Status status() const { return _status; }
95 /// Set the status to Active. Optional delay indicates number of
96 /// cycles to wait before beginning execution.
97 void activate(int delay = 1);
99 /// Set the status to Suspended.
102 /// Set the status to Unallocated.
105 /// Set the status to Halted.
110 KernelStats kernelStats;
114 RegFile regs; // correct-path register context
116 // pointer to CPU associated with this context
119 // Current instruction
122 // Index of hardware thread context on the CPU that this represents.
125 // ID of this context w.r.t. the System or Process object to which
126 // it belongs. For full-system mode, this is the system CPU ID.
131 FunctionalMemory *mem;
136 // the following two fields are redundant, since we can always
137 // look them up through the system pointer, but we'll leave them
138 // here for now for convenience
139 MemoryController *memCtrl;
140 PhysicalMemory *physmem;
146 FunctionalMemory *mem; // functional storage for process address space
148 // Address space ID. Note that this is used for TIMING cache
149 // simulation only; all functional memory accesses should use
150 // one of the FunctionalMemory pointers above.
156 * Temporary storage to pass the source address from copy_load to
158 * @todo Remove this temporary when we have a better way to do it.
162 * Temp storage for the physical source address of a copy.
163 * @todo Remove this temporary when we have a better way to do it.
165 Addr copySrcPhysAddr;
169 * number of executed instructions, for matching with syscall trace
170 * points in EIO files.
172 Counter func_exe_inst;
175 // Count failed store conditionals so we can warn of apparent
176 // application deadlock situations.
177 unsigned storeCondFailures;
179 // constructor: initialize context from given process structure
181 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
182 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
184 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
185 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
188 virtual ~ExecContext() {}
190 virtual void takeOverFrom(ExecContext *oldContext);
192 void regStats(const std::string &name);
194 void serialize(std::ostream &os);
195 void unserialize(Checkpoint *cp, const std::string §ion);
198 bool validInstAddr(Addr addr) { return true; }
199 bool validDataAddr(Addr addr) { return true; }
200 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
201 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
203 Fault translateInstReq(MemReqPtr &req)
205 return itb->translate(req);
208 Fault translateDataReadReq(MemReqPtr &req)
210 return dtb->translate(req, false);
213 Fault translateDataWriteReq(MemReqPtr &req)
215 return dtb->translate(req, true);
219 bool validInstAddr(Addr addr)
220 { return process->validInstAddr(addr); }
222 bool validDataAddr(Addr addr)
223 { return process->validDataAddr(addr); }
225 int getInstAsid() { return asid; }
226 int getDataAsid() { return asid; }
228 Fault dummyTranslation(MemReqPtr &req)
231 assert((req->vaddr >> 48 & 0xffff) == 0);
234 // put the asid in the upper 16 bits of the paddr
235 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
236 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
239 Fault translateInstReq(MemReqPtr &req)
241 return dummyTranslation(req);
243 Fault translateDataReadReq(MemReqPtr &req)
245 return dummyTranslation(req);
247 Fault translateDataWriteReq(MemReqPtr &req)
249 return dummyTranslation(req);
255 Fault read(MemReqPtr &req, T &data)
257 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
258 if (req->flags & LOCKED) {
259 MiscRegFile *cregs = &req->xc->regs.miscRegs;
260 cregs->lock_addr = req->paddr;
261 cregs->lock_flag = true;
266 error = mem->read(req, data);
272 Fault write(MemReqPtr &req, T &data)
274 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
278 // If this is a store conditional, act appropriately
279 if (req->flags & LOCKED) {
280 cregs = &req->xc->regs.miscRegs;
282 if (req->flags & UNCACHEABLE) {
283 // Don't update result register (see stq_c in isa_desc)
285 req->xc->storeCondFailures = 0;//Needed? [RGD]
287 req->result = cregs->lock_flag;
288 if (!cregs->lock_flag ||
289 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
290 cregs->lock_flag = false;
291 if (((++req->xc->storeCondFailures) % 100000) == 0) {
292 std::cerr << "Warning: "
293 << req->xc->storeCondFailures
294 << " consecutive store conditional failures "
295 << "on cpu " << req->xc->cpu_id
300 else req->xc->storeCondFailures = 0;
304 // Need to clear any locked flags on other proccessors for
305 // this address. Only do this for succsful Store Conditionals
306 // and all other stores (WH64?). Unsuccessful Store
307 // Conditionals would have returned above, and wouldn't fall
309 for (int i = 0; i < system->execContexts.size(); i++){
310 cregs = &system->execContexts[i]->regs.miscRegs;
311 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
312 cregs->lock_flag = false;
317 return mem->write(req, (T)htoa(data));
320 virtual bool misspeculating();
323 MachInst getInst() { return inst; }
325 void setInst(MachInst new_inst)
330 Fault instRead(MemReqPtr &req)
332 return mem->read(req, inst);
336 // New accessors for new decoder.
338 uint64_t readIntReg(int reg_idx)
340 return regs.intRegFile[reg_idx];
343 float readFloatRegSingle(int reg_idx)
345 return (float)regs.floatRegFile.d[reg_idx];
348 double readFloatRegDouble(int reg_idx)
350 return regs.floatRegFile.d[reg_idx];
353 uint64_t readFloatRegInt(int reg_idx)
355 return regs.floatRegFile.q[reg_idx];
358 void setIntReg(int reg_idx, uint64_t val)
360 regs.intRegFile[reg_idx] = val;
363 void setFloatRegSingle(int reg_idx, float val)
365 regs.floatRegFile.d[reg_idx] = (double)val;
368 void setFloatRegDouble(int reg_idx, double val)
370 regs.floatRegFile.d[reg_idx] = val;
373 void setFloatRegInt(int reg_idx, uint64_t val)
375 regs.floatRegFile.q[reg_idx] = val;
383 void setNextPC(uint64_t val)
390 return regs.miscRegs.uniq;
393 void setUniq(uint64_t val)
395 regs.miscRegs.uniq = val;
400 return regs.miscRegs.fpcr;
403 void setFpcr(uint64_t val)
405 regs.miscRegs.fpcr = val;
409 uint64_t readIpr(int idx, Fault &fault);
410 Fault setIpr(int idx, uint64_t val);
411 int readIntrFlag() { return regs.intrflag; }
412 void setIntrFlag(int val) { regs.intrflag = val; }
414 bool inPalMode() { return PC_PAL(regs.pc); }
415 void ev5_trap(Fault fault);
416 bool simPalCheck(int palFunc);
419 /** Meant to be more generic trap function to be
420 * called when an instruction faults.
421 * @param fault The fault generated by executing the instruction.
422 * @todo How to do this properly so it's dependent upon ISA only?
425 void trap(Fault fault);
428 IntReg getSyscallArg(int i)
430 return regs.intRegFile[ArgumentReg0 + i];
433 // used to shift args for indirect syscall
434 void setSyscallArg(int i, IntReg val)
436 regs.intRegFile[ArgumentReg0 + i] = val;
439 void setSyscallReturn(int64_t return_value)
441 // check for error condition. Alpha syscall convention is to
442 // indicate success/failure in reg a3 (r19) and put the
443 // return value itself in the standard return value reg (v0).
444 const int RegA3 = 19; // only place this is used
445 if (return_value >= 0) {
447 regs.intRegFile[RegA3] = 0;
448 regs.intRegFile[ReturnValueReg] = return_value;
450 // got an error, return details
451 regs.intRegFile[RegA3] = (IntReg) -1;
452 regs.intRegFile[ReturnValueReg] = -return_value;
458 process->syscall(this);
464 // for non-speculative execution context, spec_mode is always false
466 ExecContext::misspeculating()
471 #endif // __EXEC_CONTEXT_HH__