cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __EXEC_CONTEXT_HH__
  30 #define __EXEC_CONTEXT_HH__
  31
  32 #include "sim/host.hh"
  33 #include "mem/mem_req.hh"
  34 #include "sim/serialize.hh"
  35
  36 // forward declaration: see functional_memory.hh
  37 class FunctionalMemory;
  38 class PhysicalMemory;
  39 class BaseCPU;
  40
  41 #ifdef FULL_SYSTEM
  42
  43 #include "targetarch/alpha_memory.hh"
  44 class MemoryController;
  45
  46 #include "kern/tru64/kernel_stats.hh"
  47 #include "sim/system.hh"
  48
  49 #ifdef FS_MEASURE
  50 #include "sim/sw_context.hh"
  51 #endif
  52
  53 #else // !FULL_SYSTEM
  54
  55 #include "sim/process.hh"
  56
  57 #endif // FULL_SYSTEM
  58
  59 //
  60 // The ExecContext object represents a functional context for
  61 // instruction execution.  It incorporates everything required for
  62 // architecture-level functional simulation of a single thread.
  63 //
  64
  65 class ExecContext
  66 {
  67   public:
  68     enum Status
  69     {
  70         /// Initialized but not running yet.  All CPUs start in
  71         /// this state, but most transition to Active on cycle 1.
  72         /// In MP or SMT systems, non-primary contexts will stay
  73         /// in this state until a thread is assigned to them.
  74         Unallocated,
  75
  76         /// Running.  Instructions should be executed only when
  77         /// the context is in this state.
  78         Active,
  79
  80         /// Temporarily inactive.  Entered while waiting for
  81         /// synchronization, etc.
  82         Suspended,
  83
  84         /// Permanently shut down.  Entered when target executes
  85         /// m5exit pseudo-instruction.  When all contexts enter
  86         /// this state, the simulation will terminate.
  87         Halted
  88     };
  89
  90   private:
  91     Status _status;
  92
  93   public:
  94     Status status() const { return _status; }
  95
  96     /// Set the status to Active.  Optional delay indicates number of
  97     /// cycles to wait before beginning execution.
  98     void activate(int delay = 1);
  99
 100     /// Set the status to Suspended.
 101     void suspend();
 102
 103     /// Set the status to Unallocated.
 104     void deallocate();
 105
 106     /// Set the status to Halted.
 107     void halt();
 108
 109 #ifdef FULL_SYSTEM
 110   public:
 111     KernelStats kernelStats;
 112 #endif
 113
 114   public:
 115     RegFile regs;       // correct-path register context
 116
 117     // pointer to CPU associated with this context
 118     BaseCPU *cpu;
 119
 120     // Index of hardware thread context on the CPU that this represents.
 121     int thread_num;
 122
 123     // ID of this context w.r.t. the System or Process object to which
 124     // it belongs.  For full-system mode, this is the system CPU ID.
 125     int cpu_id;
 126
 127 #ifdef FULL_SYSTEM
 128
 129     FunctionalMemory *mem;
 130     AlphaItb *itb;
 131     AlphaDtb *dtb;
 132     System *system;
 133
 134     // the following two fields are redundant, since we can always
 135     // look them up through the system pointer, but we'll leave them
 136     // here for now for convenience
 137     MemoryController *memCtrl;
 138     PhysicalMemory *physmem;
 139
 140 #ifdef FS_MEASURE
 141     SWContext *swCtx;
 142 #endif
 143
 144 #else
 145     Process *process;
 146
 147     FunctionalMemory *mem;      // functional storage for process address space
 148
 149     // Address space ID.  Note that this is used for TIMING cache
 150     // simulation only; all functional memory accesses should use
 151     // one of the FunctionalMemory pointers above.
 152     short asid;
 153
 154 #endif
 155
 156     /**
 157      * Temporary storage to pass the source address from copy_load to
 158      * copy_store.
 159      * @todo Remove this temporary when we have a better way to do it.
 160      */
 161     Addr copySrcAddr;
 162     /**
 163      * Temp storage for the physical source address of a copy.
 164      * @todo Remove this temporary when we have a better way to do it.
 165      */
 166     Addr copySrcPhysAddr;
 167
 168
 169     /*
 170      * number of executed instructions, for matching with syscall trace
 171      * points in EIO files.
 172      */
 173     Counter func_exe_inst;
 174
 175     //
 176     // Count failed store conditionals so we can warn of apparent
 177     // application deadlock situations.
 178     unsigned storeCondFailures;
 179
 180     // constructor: initialize context from given process structure
 181 #ifdef FULL_SYSTEM
 182     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 183                 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
 184 #else
 185     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 186     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 187                 int _asid);
 188 #endif
 189     virtual ~ExecContext() {}
 190
 191     virtual void takeOverFrom(ExecContext *oldContext);
 192
 193     void regStats(const std::string &name);
 194
 195     void serialize(std::ostream &os);
 196     void unserialize(Checkpoint *cp, const std::string &section);
 197
 198 #ifdef FULL_SYSTEM
 199     bool validInstAddr(Addr addr) { return true; }
 200     bool validDataAddr(Addr addr) { return true; }
 201     int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
 202     int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
 203
 204     Fault translateInstReq(MemReqPtr &req)
 205     {
 206         return itb->translate(req);
 207     }
 208
 209     Fault translateDataReadReq(MemReqPtr &req)
 210     {
 211         return dtb->translate(req, false);
 212     }
 213
 214     Fault translateDataWriteReq(MemReqPtr &req)
 215     {
 216         return dtb->translate(req, true);
 217     }
 218
 219 #else
 220     bool validInstAddr(Addr addr)
 221     { return process->validInstAddr(addr); }
 222
 223     bool validDataAddr(Addr addr)
 224     { return process->validDataAddr(addr); }
 225
 226     int getInstAsid() { return asid; }
 227     int getDataAsid() { return asid; }
 228
 229     Fault dummyTranslation(MemReqPtr &req)
 230     {
 231 #if 0
 232         assert((req->vaddr >> 48 & 0xffff) == 0);
 233 #endif
 234
 235         // put the asid in the upper 16 bits of the paddr
 236         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 237         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 238         return No_Fault;
 239     }
 240     Fault translateInstReq(MemReqPtr &req)
 241     {
 242         return dummyTranslation(req);
 243     }
 244     Fault translateDataReadReq(MemReqPtr &req)
 245     {
 246         return dummyTranslation(req);
 247     }
 248     Fault translateDataWriteReq(MemReqPtr &req)
 249     {
 250         return dummyTranslation(req);
 251     }
 252
 253 #endif
 254
 255     template <class T>
 256     Fault read(MemReqPtr &req, T &data)
 257     {
 258 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 259         if (req->flags & LOCKED) {
 260             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 261             cregs->lock_addr = req->paddr;
 262             cregs->lock_flag = true;
 263         }
 264 #endif
 265         return mem->read(req, data);
 266     }
 267
 268     template <class T>
 269     Fault write(MemReqPtr &req, T &data)
 270     {
 271 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 272
 273         MiscRegFile *cregs;
 274
 275         // If this is a store conditional, act appropriately
 276         if (req->flags & LOCKED) {
 277             cregs = &req->xc->regs.miscRegs;
 278
 279             if (req->flags & UNCACHEABLE) {
 280                 // Don't update result register (see stq_c in isa_desc)
 281                 req->result = 2;
 282                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 283             } else {
 284                 req->result = cregs->lock_flag;
 285                 if (!cregs->lock_flag ||
 286                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 287                     cregs->lock_flag = false;
 288                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 289                         std::cerr << "Warning: "
 290                                   << req->xc->storeCondFailures
 291                                   << " consecutive store conditional failures "
 292                                   << "on cpu " << req->xc->cpu_id
 293                                   << std::endl;
 294                     }
 295                     return No_Fault;
 296                 }
 297                 else req->xc->storeCondFailures = 0;
 298             }
 299         }
 300
 301         // Need to clear any locked flags on other proccessors for
 302         // this address.  Only do this for succsful Store Conditionals
 303         // and all other stores (WH64?).  Unsuccessful Store
 304         // Conditionals would have returned above, and wouldn't fall
 305         // through.
 306         for (int i = 0; i < system->execContexts.size(); i++){
 307             cregs = &system->execContexts[i]->regs.miscRegs;
 308             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 309                 cregs->lock_flag = false;
 310             }
 311         }
 312
 313 #endif
 314         return mem->write(req, data);
 315     }
 316
 317     virtual bool misspeculating();
 318
 319
 320     //
 321     // New accessors for new decoder.
 322     //
 323     uint64_t readIntReg(int reg_idx)
 324     {
 325         return regs.intRegFile[reg_idx];
 326     }
 327
 328     float readFloatRegSingle(int reg_idx)
 329     {
 330         return (float)regs.floatRegFile.d[reg_idx];
 331     }
 332
 333     double readFloatRegDouble(int reg_idx)
 334     {
 335         return regs.floatRegFile.d[reg_idx];
 336     }
 337
 338     uint64_t readFloatRegInt(int reg_idx)
 339     {
 340         return regs.floatRegFile.q[reg_idx];
 341     }
 342
 343     void setIntReg(int reg_idx, uint64_t val)
 344     {
 345         regs.intRegFile[reg_idx] = val;
 346     }
 347
 348     void setFloatRegSingle(int reg_idx, float val)
 349     {
 350         regs.floatRegFile.d[reg_idx] = (double)val;
 351     }
 352
 353     void setFloatRegDouble(int reg_idx, double val)
 354     {
 355         regs.floatRegFile.d[reg_idx] = val;
 356     }
 357
 358     void setFloatRegInt(int reg_idx, uint64_t val)
 359     {
 360         regs.floatRegFile.q[reg_idx] = val;
 361     }
 362
 363     uint64_t readPC()
 364     {
 365         return regs.pc;
 366     }
 367
 368     void setNextPC(uint64_t val)
 369     {
 370         regs.npc = val;
 371     }
 372
 373     uint64_t readUniq()
 374     {
 375         return regs.miscRegs.uniq;
 376     }
 377
 378     void setUniq(uint64_t val)
 379     {
 380         regs.miscRegs.uniq = val;
 381     }
 382
 383     uint64_t readFpcr()
 384     {
 385         return regs.miscRegs.fpcr;
 386     }
 387
 388     void setFpcr(uint64_t val)
 389     {
 390         regs.miscRegs.fpcr = val;
 391     }
 392
 393 #ifdef FULL_SYSTEM
 394     uint64_t readIpr(int idx, Fault &fault);
 395     Fault setIpr(int idx, uint64_t val);
 396     Fault hwrei();
 397     void ev5_trap(Fault fault);
 398     bool simPalCheck(int palFunc);
 399 #endif
 400
 401 #ifndef FULL_SYSTEM
 402     IntReg getSyscallArg(int i)
 403     {
 404         return regs.intRegFile[ArgumentReg0 + i];
 405     }
 406
 407     // used to shift args for indirect syscall
 408     void setSyscallArg(int i, IntReg val)
 409     {
 410         regs.intRegFile[ArgumentReg0 + i] = val;
 411     }
 412
 413     void setSyscallReturn(int64_t return_value)
 414     {
 415         // check for error condition.  Alpha syscall convention is to
 416         // indicate success/failure in reg a3 (r19) and put the
 417         // return value itself in the standard return value reg (v0).
 418         const int RegA3 = 19;   // only place this is used
 419         if (return_value >= 0) {
 420             // no error
 421             regs.intRegFile[RegA3] = 0;
 422             regs.intRegFile[ReturnValueReg] = return_value;
 423         } else {
 424             // got an error, return details
 425             regs.intRegFile[RegA3] = (IntReg) -1;
 426             regs.intRegFile[ReturnValueReg] = -return_value;
 427         }
 428     }
 429
 430     void syscall()
 431     {
 432         process->syscall(this);
 433     }
 434 #endif
 435 };
 436
 437
 438 // for non-speculative execution context, spec_mode is always false
 439 inline bool
 440 ExecContext::misspeculating()
 441 {
 442     return false;
 443 }
 444
 445 #endif // __EXEC_CONTEXT_HH__