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29 #ifndef __EXEC_CONTEXT_HH__
30 #define __EXEC_CONTEXT_HH__
32 #include "sim/host.hh"
33 #include "mem/mem_req.hh"
34 #include "sim/serialize.hh"
36 // forward declaration: see functional_memory.hh
37 class FunctionalMemory;
43 #include "targetarch/alpha_memory.hh"
44 class MemoryController;
46 #include "kern/tru64/kernel_stats.hh"
47 #include "sim/system.hh"
50 #include "sim/sw_context.hh"
55 #include "sim/process.hh"
60 // The ExecContext object represents a functional context for
61 // instruction execution. It incorporates everything required for
62 // architecture-level functional simulation of a single thread.
70 /// Initialized but not running yet. All CPUs start in
71 /// this state, but most transition to Active on cycle 1.
72 /// In MP or SMT systems, non-primary contexts will stay
73 /// in this state until a thread is assigned to them.
76 /// Running. Instructions should be executed only when
77 /// the context is in this state.
80 /// Temporarily inactive. Entered while waiting for
81 /// synchronization, etc.
84 /// Permanently shut down. Entered when target executes
85 /// m5exit pseudo-instruction. When all contexts enter
86 /// this state, the simulation will terminate.
94 Status status() const { return _status; }
96 /// Set the status to Active. Optional delay indicates number of
97 /// cycles to wait before beginning execution.
98 void activate(int delay = 1);
100 /// Set the status to Suspended.
103 /// Set the status to Unallocated.
106 /// Set the status to Halted.
111 KernelStats kernelStats;
115 RegFile regs; // correct-path register context
117 // pointer to CPU associated with this context
120 // Index of hardware thread context on the CPU that this represents.
123 // ID of this context w.r.t. the System or Process object to which
124 // it belongs. For full-system mode, this is the system CPU ID.
129 FunctionalMemory *mem;
134 // the following two fields are redundant, since we can always
135 // look them up through the system pointer, but we'll leave them
136 // here for now for convenience
137 MemoryController *memCtrl;
138 PhysicalMemory *physmem;
147 FunctionalMemory *mem; // functional storage for process address space
149 // Address space ID. Note that this is used for TIMING cache
150 // simulation only; all functional memory accesses should use
151 // one of the FunctionalMemory pointers above.
158 * number of executed instructions, for matching with syscall trace
159 * points in EIO files.
161 Counter func_exe_inst;
164 // Count failed store conditionals so we can warn of apparent
165 // application deadlock situations.
166 unsigned storeCondFailures;
168 // constructor: initialize context from given process structure
170 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
171 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
173 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
174 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
177 virtual ~ExecContext() {}
179 virtual void takeOverFrom(ExecContext *oldContext);
181 void regStats(const std::string &name);
183 void serialize(std::ostream &os);
184 void unserialize(Checkpoint *cp, const std::string §ion);
187 bool validInstAddr(Addr addr) { return true; }
188 bool validDataAddr(Addr addr) { return true; }
189 int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
190 int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
192 Fault translateInstReq(MemReqPtr &req)
194 return itb->translate(req);
197 Fault translateDataReadReq(MemReqPtr &req)
199 return dtb->translate(req, false);
202 Fault translateDataWriteReq(MemReqPtr &req)
204 return dtb->translate(req, true);
208 bool validInstAddr(Addr addr)
209 { return process->validInstAddr(addr); }
211 bool validDataAddr(Addr addr)
212 { return process->validDataAddr(addr); }
214 int getInstAsid() { return asid; }
215 int getDataAsid() { return asid; }
217 Fault dummyTranslation(MemReqPtr &req)
220 assert((req->vaddr >> 48 & 0xffff) == 0);
223 // put the asid in the upper 16 bits of the paddr
224 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
225 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
228 Fault translateInstReq(MemReqPtr &req)
230 return dummyTranslation(req);
232 Fault translateDataReadReq(MemReqPtr &req)
234 return dummyTranslation(req);
236 Fault translateDataWriteReq(MemReqPtr &req)
238 return dummyTranslation(req);
244 Fault read(MemReqPtr &req, T &data)
246 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
247 if (req->flags & LOCKED) {
248 MiscRegFile *cregs = &req->xc->regs.miscRegs;
249 cregs->lock_addr = req->paddr;
250 cregs->lock_flag = true;
253 return mem->read(req, data);
257 Fault write(MemReqPtr &req, T &data)
259 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
263 // If this is a store conditional, act appropriately
264 if (req->flags & LOCKED) {
265 cregs = &req->xc->regs.miscRegs;
267 if (req->flags & UNCACHEABLE) {
268 // Don't update result register (see stq_c in isa_desc)
270 req->xc->storeCondFailures = 0;//Needed? [RGD]
272 req->result = cregs->lock_flag;
273 if (!cregs->lock_flag ||
274 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
275 cregs->lock_flag = false;
276 if (((++req->xc->storeCondFailures) % 100000) == 0) {
277 std::cerr << "Warning: "
278 << req->xc->storeCondFailures
279 << " consecutive store conditional failures "
280 << "on cpu " << req->xc->cpu_id
285 else req->xc->storeCondFailures = 0;
289 // Need to clear any locked flags on other proccessors for
290 // this address. Only do this for succsful Store Conditionals
291 // and all other stores (WH64?). Unsuccessful Store
292 // Conditionals would have returned above, and wouldn't fall
294 for (int i = 0; i < system->execContexts.size(); i++){
295 cregs = &system->execContexts[i]->regs.miscRegs;
296 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
297 cregs->lock_flag = false;
302 return mem->write(req, data);
305 virtual bool misspeculating();
309 // New accessors for new decoder.
311 uint64_t readIntReg(int reg_idx)
313 return regs.intRegFile[reg_idx];
316 float readFloatRegSingle(int reg_idx)
318 return (float)regs.floatRegFile.d[reg_idx];
321 double readFloatRegDouble(int reg_idx)
323 return regs.floatRegFile.d[reg_idx];
326 uint64_t readFloatRegInt(int reg_idx)
328 return regs.floatRegFile.q[reg_idx];
331 void setIntReg(int reg_idx, uint64_t val)
333 regs.intRegFile[reg_idx] = val;
336 void setFloatRegSingle(int reg_idx, float val)
338 regs.floatRegFile.d[reg_idx] = (double)val;
341 void setFloatRegDouble(int reg_idx, double val)
343 regs.floatRegFile.d[reg_idx] = val;
346 void setFloatRegInt(int reg_idx, uint64_t val)
348 regs.floatRegFile.q[reg_idx] = val;
356 void setNextPC(uint64_t val)
363 return regs.miscRegs.uniq;
366 void setUniq(uint64_t val)
368 regs.miscRegs.uniq = val;
373 return regs.miscRegs.fpcr;
376 void setFpcr(uint64_t val)
378 regs.miscRegs.fpcr = val;
382 uint64_t readIpr(int idx, Fault &fault);
383 Fault setIpr(int idx, uint64_t val);
385 void ev5_trap(Fault fault);
386 bool simPalCheck(int palFunc);
390 IntReg getSyscallArg(int i)
392 return regs.intRegFile[ArgumentReg0 + i];
395 // used to shift args for indirect syscall
396 void setSyscallArg(int i, IntReg val)
398 regs.intRegFile[ArgumentReg0 + i] = val;
401 void setSyscallReturn(int64_t return_value)
403 // check for error condition. Alpha syscall convention is to
404 // indicate success/failure in reg a3 (r19) and put the
405 // return value itself in the standard return value reg (v0).
406 const int RegA3 = 19; // only place this is used
407 if (return_value >= 0) {
409 regs.intRegFile[RegA3] = 0;
410 regs.intRegFile[ReturnValueReg] = return_value;
412 // got an error, return details
413 regs.intRegFile[RegA3] = (IntReg) -1;
414 regs.intRegFile[ReturnValueReg] = -return_value;
420 process->syscall(this);
426 // for non-speculative execution context, spec_mode is always false
428 ExecContext::misspeculating()
433 #endif // __EXEC_CONTEXT_HH__