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29 #ifndef __CPU_EXEC_CONTEXT_HH__
30 #define __CPU_EXEC_CONTEXT_HH__
32 #include "config/full_system.hh"
33 #include "mem/functional/functional.hh"
34 #include "mem/mem_req.hh"
35 #include "sim/host.hh"
36 #include "sim/serialize.hh"
37 #include "arch/isa_traits.hh"
38 #include "sim/byteswap.hh"
40 // forward declaration: see functional_memory.hh
41 class FunctionalMemory;
47 #include "sim/system.hh"
48 #include "targetarch/alpha_memory.hh"
50 class FunctionProfile;
52 class MemoryController;
53 namespace Kernel { class Binning; class Statistics; }
57 #include "sim/process.hh"
62 // The ExecContext object represents a functional context for
63 // instruction execution. It incorporates everything required for
64 // architecture-level functional simulation of a single thread.
72 /// Initialized but not running yet. All CPUs start in
73 /// this state, but most transition to Active on cycle 1.
74 /// In MP or SMT systems, non-primary contexts will stay
75 /// in this state until a thread is assigned to them.
78 /// Running. Instructions should be executed only when
79 /// the context is in this state.
82 /// Temporarily inactive. Entered while waiting for
83 /// synchronization, etc.
86 /// Permanently shut down. Entered when target executes
87 /// m5exit pseudo-instruction. When all contexts enter
88 /// this state, the simulation will terminate.
96 Status status() const { return _status; }
98 /// Set the status to Active. Optional delay indicates number of
99 /// cycles to wait before beginning execution.
100 void activate(int delay = 1);
102 /// Set the status to Suspended.
105 /// Set the status to Unallocated.
108 /// Set the status to Halted.
112 RegFile regs; // correct-path register context
114 // pointer to CPU associated with this context
117 // Current instruction
120 // Index of hardware thread context on the CPU that this represents.
123 // ID of this context w.r.t. the System or Process object to which
124 // it belongs. For full-system mode, this is the system CPU ID.
128 FunctionalMemory *mem;
133 // the following two fields are redundant, since we can always
134 // look them up through the system pointer, but we'll leave them
135 // here for now for convenience
136 MemoryController *memctrl;
137 PhysicalMemory *physmem;
139 Kernel::Binning *kernelBinning;
140 Kernel::Statistics *kernelStats;
144 FunctionProfile *profile;
145 ProfileNode *profileNode;
147 void dumpFuncProfile();
152 FunctionalMemory *mem; // functional storage for process address space
154 // Address space ID. Note that this is used for TIMING cache
155 // simulation only; all functional memory accesses should use
156 // one of the FunctionalMemory pointers above.
162 * Temporary storage to pass the source address from copy_load to
164 * @todo Remove this temporary when we have a better way to do it.
168 * Temp storage for the physical source address of a copy.
169 * @todo Remove this temporary when we have a better way to do it.
171 Addr copySrcPhysAddr;
175 * number of executed instructions, for matching with syscall trace
176 * points in EIO files.
178 Counter func_exe_inst;
181 // Count failed store conditionals so we can warn of apparent
182 // application deadlock situations.
183 unsigned storeCondFailures;
185 // constructor: initialize context from given process structure
187 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
188 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
190 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
191 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
194 virtual ~ExecContext();
196 virtual void takeOverFrom(ExecContext *oldContext);
198 void regStats(const std::string &name);
200 void serialize(std::ostream &os);
201 void unserialize(Checkpoint *cp, const std::string §ion);
204 bool validInstAddr(Addr addr) { return true; }
205 bool validDataAddr(Addr addr) { return true; }
206 int getInstAsid() { return regs.instAsid(); }
207 int getDataAsid() { return regs.dataAsid(); }
209 Fault * translateInstReq(MemReqPtr &req)
211 return itb->translate(req);
214 Fault * translateDataReadReq(MemReqPtr &req)
216 return dtb->translate(req, false);
219 Fault * translateDataWriteReq(MemReqPtr &req)
221 return dtb->translate(req, true);
225 bool validInstAddr(Addr addr)
226 { return process->validInstAddr(addr); }
228 bool validDataAddr(Addr addr)
229 { return process->validDataAddr(addr); }
231 int getInstAsid() { return asid; }
232 int getDataAsid() { return asid; }
234 Fault * dummyTranslation(MemReqPtr &req)
237 assert((req->vaddr >> 48 & 0xffff) == 0);
240 // put the asid in the upper 16 bits of the paddr
241 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
242 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
245 Fault * translateInstReq(MemReqPtr &req)
247 return dummyTranslation(req);
249 Fault * translateDataReadReq(MemReqPtr &req)
251 return dummyTranslation(req);
253 Fault * translateDataWriteReq(MemReqPtr &req)
255 return dummyTranslation(req);
261 Fault * read(MemReqPtr &req, T &data)
263 #if FULL_SYSTEM && defined(TARGET_ALPHA)
264 if (req->flags & LOCKED) {
265 MiscRegFile *cregs = &req->xc->regs.miscRegs;
266 cregs->lock_addr = req->paddr;
267 cregs->lock_flag = true;
272 error = mem->read(req, data);
273 data = LittleEndianGuest::gtoh(data);
278 Fault * write(MemReqPtr &req, T &data)
280 #if FULL_SYSTEM && defined(TARGET_ALPHA)
284 // If this is a store conditional, act appropriately
285 if (req->flags & LOCKED) {
286 cregs = &req->xc->regs.miscRegs;
288 if (req->flags & UNCACHEABLE) {
289 // Don't update result register (see stq_c in isa_desc)
291 req->xc->storeCondFailures = 0;//Needed? [RGD]
293 req->result = cregs->lock_flag;
294 if (!cregs->lock_flag ||
295 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
296 cregs->lock_flag = false;
297 if (((++req->xc->storeCondFailures) % 100000) == 0) {
298 std::cerr << "Warning: "
299 << req->xc->storeCondFailures
300 << " consecutive store conditional failures "
301 << "on cpu " << req->xc->cpu_id
306 else req->xc->storeCondFailures = 0;
310 // Need to clear any locked flags on other proccessors for
311 // this address. Only do this for succsful Store Conditionals
312 // and all other stores (WH64?). Unsuccessful Store
313 // Conditionals would have returned above, and wouldn't fall
315 for (int i = 0; i < system->execContexts.size(); i++){
316 cregs = &system->execContexts[i]->regs.miscRegs;
317 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
318 cregs->lock_flag = false;
323 return mem->write(req, (T)LittleEndianGuest::htog(data));
326 virtual bool misspeculating();
329 MachInst getInst() { return inst; }
331 void setInst(MachInst new_inst)
336 Fault * instRead(MemReqPtr &req)
338 return mem->read(req, inst);
342 // New accessors for new decoder.
344 uint64_t readIntReg(int reg_idx)
346 return regs.intRegFile[reg_idx];
349 float readFloatRegSingle(int reg_idx)
351 return (float)regs.floatRegFile.d[reg_idx];
354 double readFloatRegDouble(int reg_idx)
356 return regs.floatRegFile.d[reg_idx];
359 uint64_t readFloatRegInt(int reg_idx)
361 return regs.floatRegFile.q[reg_idx];
364 void setIntReg(int reg_idx, uint64_t val)
366 regs.intRegFile[reg_idx] = val;
369 void setFloatRegSingle(int reg_idx, float val)
371 regs.floatRegFile.d[reg_idx] = (double)val;
374 void setFloatRegDouble(int reg_idx, double val)
376 regs.floatRegFile.d[reg_idx] = val;
379 void setFloatRegInt(int reg_idx, uint64_t val)
381 regs.floatRegFile.q[reg_idx] = val;
389 void setNextPC(uint64_t val)
396 return regs.miscRegs.uniq;
399 void setUniq(uint64_t val)
401 regs.miscRegs.uniq = val;
406 return regs.miscRegs.fpcr;
409 void setFpcr(uint64_t val)
411 regs.miscRegs.fpcr = val;
415 uint64_t readIpr(int idx, Fault * &fault);
416 Fault * setIpr(int idx, uint64_t val);
417 int readIntrFlag() { return regs.intrflag; }
418 void setIntrFlag(int val) { regs.intrflag = val; }
420 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
421 void ev5_trap(Fault * fault);
422 bool simPalCheck(int palFunc);
425 /** Meant to be more generic trap function to be
426 * called when an instruction faults.
427 * @param fault The fault generated by executing the instruction.
428 * @todo How to do this properly so it's dependent upon ISA only?
431 void trap(Fault * fault);
434 IntReg getSyscallArg(int i)
436 return regs.intRegFile[ArgumentReg0 + i];
439 // used to shift args for indirect syscall
440 void setSyscallArg(int i, IntReg val)
442 regs.intRegFile[ArgumentReg0 + i] = val;
445 void setSyscallReturn(SyscallReturn return_value)
447 // check for error condition. Alpha syscall convention is to
448 // indicate success/failure in reg a3 (r19) and put the
449 // return value itself in the standard return value reg (v0).
450 const int RegA3 = 19; // only place this is used
451 if (return_value.successful()) {
453 regs.intRegFile[RegA3] = 0;
454 regs.intRegFile[ReturnValueReg] = return_value.value();
456 // got an error, return details
457 regs.intRegFile[RegA3] = (IntReg) -1;
458 regs.intRegFile[ReturnValueReg] = -return_value.value();
464 process->syscall(this);
470 // for non-speculative execution context, spec_mode is always false
472 ExecContext::misspeculating()
477 #endif // __CPU_EXEC_CONTEXT_HH__