cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __EXEC_CONTEXT_HH__
  30 #define __EXEC_CONTEXT_HH__
  31
  32 #include "sim/host.hh"
  33 #include "mem/mem_req.hh"
  34 #include "sim/serialize.hh"
  35
  36 // forward declaration: see functional_memory.hh
  37 class FunctionalMemory;
  38 class PhysicalMemory;
  39 class BaseCPU;
  40
  41 #ifdef FULL_SYSTEM
  42
  43 #include "targetarch/alpha_memory.hh"
  44 class MemoryController;
  45
  46 #include "kern/tru64/kernel_stats.hh"
  47 #include "sim/system.hh"
  48 #include "sim/sw_context.hh"
  49
  50 #else // !FULL_SYSTEM
  51
  52 #include "sim/process.hh"
  53
  54 #endif // FULL_SYSTEM
  55
  56 //
  57 // The ExecContext object represents a functional context for
  58 // instruction execution.  It incorporates everything required for
  59 // architecture-level functional simulation of a single thread.
  60 //
  61
  62 class ExecContext
  63 {
  64   public:
  65     enum Status
  66     {
  67         /// Initialized but not running yet.  All CPUs start in
  68         /// this state, but most transition to Active on cycle 1.
  69         /// In MP or SMT systems, non-primary contexts will stay
  70         /// in this state until a thread is assigned to them.
  71         Unallocated,
  72
  73         /// Running.  Instructions should be executed only when
  74         /// the context is in this state.
  75         Active,
  76
  77         /// Temporarily inactive.  Entered while waiting for
  78         /// synchronization, etc.
  79         Suspended,
  80
  81         /// Permanently shut down.  Entered when target executes
  82         /// m5exit pseudo-instruction.  When all contexts enter
  83         /// this state, the simulation will terminate.
  84         Halted
  85     };
  86
  87   private:
  88     Status _status;
  89
  90   public:
  91     Status status() const { return _status; }
  92
  93     /// Set the status to Active.  Optional delay indicates number of
  94     /// cycles to wait before beginning execution.
  95     void activate(int delay = 1);
  96
  97     /// Set the status to Suspended.
  98     void suspend();
  99
 100     /// Set the status to Unallocated.
 101     void deallocate();
 102
 103     /// Set the status to Halted.
 104     void halt();
 105
 106 #ifdef FULL_SYSTEM
 107   public:
 108     KernelStats kernelStats;
 109 #endif
 110
 111   public:
 112     RegFile regs;       // correct-path register context
 113
 114     // pointer to CPU associated with this context
 115     BaseCPU *cpu;
 116
 117     // Index of hardware thread context on the CPU that this represents.
 118     int thread_num;
 119
 120     // ID of this context w.r.t. the System or Process object to which
 121     // it belongs.  For full-system mode, this is the system CPU ID.
 122     int cpu_id;
 123
 124 #ifdef FULL_SYSTEM
 125
 126     FunctionalMemory *mem;
 127     AlphaItb *itb;
 128     AlphaDtb *dtb;
 129     System *system;
 130
 131     // the following two fields are redundant, since we can always
 132     // look them up through the system pointer, but we'll leave them
 133     // here for now for convenience
 134     MemoryController *memCtrl;
 135     PhysicalMemory *physmem;
 136
 137     SWContext *swCtx;
 138 #else
 139     Process *process;
 140
 141     FunctionalMemory *mem;      // functional storage for process address space
 142
 143     // Address space ID.  Note that this is used for TIMING cache
 144     // simulation only; all functional memory accesses should use
 145     // one of the FunctionalMemory pointers above.
 146     short asid;
 147
 148 #endif
 149
 150     /**
 151      * Temporary storage to pass the source address from copy_load to
 152      * copy_store.
 153      * @todo Remove this temporary when we have a better way to do it.
 154      */
 155     Addr copySrcAddr;
 156     /**
 157      * Temp storage for the physical source address of a copy.
 158      * @todo Remove this temporary when we have a better way to do it.
 159      */
 160     Addr copySrcPhysAddr;
 161
 162
 163     /*
 164      * number of executed instructions, for matching with syscall trace
 165      * points in EIO files.
 166      */
 167     Counter func_exe_inst;
 168
 169     //
 170     // Count failed store conditionals so we can warn of apparent
 171     // application deadlock situations.
 172     unsigned storeCondFailures;
 173
 174     // constructor: initialize context from given process structure
 175 #ifdef FULL_SYSTEM
 176     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 177                 AlphaItb *_itb, AlphaDtb *_dtb, FunctionalMemory *_dem);
 178 #else
 179     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 180     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 181                 int _asid);
 182 #endif
 183     virtual ~ExecContext() {}
 184
 185     virtual void takeOverFrom(ExecContext *oldContext);
 186
 187     void regStats(const std::string &name);
 188
 189     void serialize(std::ostream &os);
 190     void unserialize(Checkpoint *cp, const std::string &section);
 191
 192 #ifdef FULL_SYSTEM
 193     bool validInstAddr(Addr addr) { return true; }
 194     bool validDataAddr(Addr addr) { return true; }
 195     int getInstAsid() { return ITB_ASN_ASN(regs.ipr[TheISA::IPR_ITB_ASN]); }
 196     int getDataAsid() { return DTB_ASN_ASN(regs.ipr[TheISA::IPR_DTB_ASN]); }
 197
 198     Fault translateInstReq(MemReqPtr &req)
 199     {
 200         return itb->translate(req);
 201     }
 202
 203     Fault translateDataReadReq(MemReqPtr &req)
 204     {
 205         return dtb->translate(req, false);
 206     }
 207
 208     Fault translateDataWriteReq(MemReqPtr &req)
 209     {
 210         return dtb->translate(req, true);
 211     }
 212
 213 #else
 214     bool validInstAddr(Addr addr)
 215     { return process->validInstAddr(addr); }
 216
 217     bool validDataAddr(Addr addr)
 218     { return process->validDataAddr(addr); }
 219
 220     int getInstAsid() { return asid; }
 221     int getDataAsid() { return asid; }
 222
 223     Fault dummyTranslation(MemReqPtr &req)
 224     {
 225 #if 0
 226         assert((req->vaddr >> 48 & 0xffff) == 0);
 227 #endif
 228
 229         // put the asid in the upper 16 bits of the paddr
 230         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 231         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 232         return No_Fault;
 233     }
 234     Fault translateInstReq(MemReqPtr &req)
 235     {
 236         return dummyTranslation(req);
 237     }
 238     Fault translateDataReadReq(MemReqPtr &req)
 239     {
 240         return dummyTranslation(req);
 241     }
 242     Fault translateDataWriteReq(MemReqPtr &req)
 243     {
 244         return dummyTranslation(req);
 245     }
 246
 247 #endif
 248
 249     template <class T>
 250     Fault read(MemReqPtr &req, T &data)
 251     {
 252 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 253         if (req->flags & LOCKED) {
 254             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 255             cregs->lock_addr = req->paddr;
 256             cregs->lock_flag = true;
 257         }
 258 #endif
 259         return mem->read(req, data);
 260     }
 261
 262     template <class T>
 263     Fault write(MemReqPtr &req, T &data)
 264     {
 265 #if defined(TARGET_ALPHA) && defined(FULL_SYSTEM)
 266
 267         MiscRegFile *cregs;
 268
 269         // If this is a store conditional, act appropriately
 270         if (req->flags & LOCKED) {
 271             cregs = &req->xc->regs.miscRegs;
 272
 273             if (req->flags & UNCACHEABLE) {
 274                 // Don't update result register (see stq_c in isa_desc)
 275                 req->result = 2;
 276                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 277             } else {
 278                 req->result = cregs->lock_flag;
 279                 if (!cregs->lock_flag ||
 280                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 281                     cregs->lock_flag = false;
 282                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 283                         std::cerr << "Warning: "
 284                                   << req->xc->storeCondFailures
 285                                   << " consecutive store conditional failures "
 286                                   << "on cpu " << req->xc->cpu_id
 287                                   << std::endl;
 288                     }
 289                     return No_Fault;
 290                 }
 291                 else req->xc->storeCondFailures = 0;
 292             }
 293         }
 294
 295         // Need to clear any locked flags on other proccessors for
 296         // this address.  Only do this for succsful Store Conditionals
 297         // and all other stores (WH64?).  Unsuccessful Store
 298         // Conditionals would have returned above, and wouldn't fall
 299         // through.
 300         for (int i = 0; i < system->execContexts.size(); i++){
 301             cregs = &system->execContexts[i]->regs.miscRegs;
 302             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 303                 cregs->lock_flag = false;
 304             }
 305         }
 306
 307 #endif
 308         return mem->write(req, data);
 309     }
 310
 311     virtual bool misspeculating();
 312
 313
 314     //
 315     // New accessors for new decoder.
 316     //
 317     uint64_t readIntReg(int reg_idx)
 318     {
 319         return regs.intRegFile[reg_idx];
 320     }
 321
 322     float readFloatRegSingle(int reg_idx)
 323     {
 324         return (float)regs.floatRegFile.d[reg_idx];
 325     }
 326
 327     double readFloatRegDouble(int reg_idx)
 328     {
 329         return regs.floatRegFile.d[reg_idx];
 330     }
 331
 332     uint64_t readFloatRegInt(int reg_idx)
 333     {
 334         return regs.floatRegFile.q[reg_idx];
 335     }
 336
 337     void setIntReg(int reg_idx, uint64_t val)
 338     {
 339         regs.intRegFile[reg_idx] = val;
 340     }
 341
 342     void setFloatRegSingle(int reg_idx, float val)
 343     {
 344         regs.floatRegFile.d[reg_idx] = (double)val;
 345     }
 346
 347     void setFloatRegDouble(int reg_idx, double val)
 348     {
 349         regs.floatRegFile.d[reg_idx] = val;
 350     }
 351
 352     void setFloatRegInt(int reg_idx, uint64_t val)
 353     {
 354         regs.floatRegFile.q[reg_idx] = val;
 355     }
 356
 357     uint64_t readPC()
 358     {
 359         return regs.pc;
 360     }
 361
 362     void setNextPC(uint64_t val)
 363     {
 364         regs.npc = val;
 365     }
 366
 367     uint64_t readUniq()
 368     {
 369         return regs.miscRegs.uniq;
 370     }
 371
 372     void setUniq(uint64_t val)
 373     {
 374         regs.miscRegs.uniq = val;
 375     }
 376
 377     uint64_t readFpcr()
 378     {
 379         return regs.miscRegs.fpcr;
 380     }
 381
 382     void setFpcr(uint64_t val)
 383     {
 384         regs.miscRegs.fpcr = val;
 385     }
 386
 387 #ifdef FULL_SYSTEM
 388     uint64_t readIpr(int idx, Fault &fault);
 389     Fault setIpr(int idx, uint64_t val);
 390     Fault hwrei();
 391     void ev5_trap(Fault fault);
 392     bool simPalCheck(int palFunc);
 393 #endif
 394
 395 #ifndef FULL_SYSTEM
 396     IntReg getSyscallArg(int i)
 397     {
 398         return regs.intRegFile[ArgumentReg0 + i];
 399     }
 400
 401     // used to shift args for indirect syscall
 402     void setSyscallArg(int i, IntReg val)
 403     {
 404         regs.intRegFile[ArgumentReg0 + i] = val;
 405     }
 406
 407     void setSyscallReturn(int64_t return_value)
 408     {
 409         // check for error condition.  Alpha syscall convention is to
 410         // indicate success/failure in reg a3 (r19) and put the
 411         // return value itself in the standard return value reg (v0).
 412         const int RegA3 = 19;   // only place this is used
 413         if (return_value >= 0) {
 414             // no error
 415             regs.intRegFile[RegA3] = 0;
 416             regs.intRegFile[ReturnValueReg] = return_value;
 417         } else {
 418             // got an error, return details
 419             regs.intRegFile[RegA3] = (IntReg) -1;
 420             regs.intRegFile[ReturnValueReg] = -return_value;
 421         }
 422     }
 423
 424     void syscall()
 425     {
 426         process->syscall(this);
 427     }
 428 #endif
 429 };
 430
 431
 432 // for non-speculative execution context, spec_mode is always false
 433 inline bool
 434 ExecContext::misspeculating()
 435 {
 436     return false;
 437 }
 438
 439 #endif // __EXEC_CONTEXT_HH__