cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
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   5  * Redistribution and use in source and binary forms, with or without
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   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_EXEC_CONTEXT_HH__
  30 #define __CPU_EXEC_CONTEXT_HH__
  31
  32 #include "config/full_system.hh"
  33 #include "mem/functional/functional.hh"
  34 #include "mem/mem_req.hh"
  35 #include "sim/host.hh"
  36 #include "sim/serialize.hh"
  37 #include "arch/isa_traits.hh"
  38 #include "sim/byteswap.hh"
  39
  40 // forward declaration: see functional_memory.hh
  41 class FunctionalMemory;
  42 class PhysicalMemory;
  43 class BaseCPU;
  44
  45 #if FULL_SYSTEM
  46
  47 #include "sim/system.hh"
  48 #include "targetarch/alpha_memory.hh"
  49
  50 class FunctionProfile;
  51 class ProfileNode;
  52 class MemoryController;
  53 namespace Kernel { class Binning; class Statistics; }
  54
  55 #else // !FULL_SYSTEM
  56
  57 #include "sim/process.hh"
  58
  59 #endif // FULL_SYSTEM
  60
  61 //
  62 // The ExecContext object represents a functional context for
  63 // instruction execution.  It incorporates everything required for
  64 // architecture-level functional simulation of a single thread.
  65 //
  66
  67 class ExecContext
  68 {
  69   public:
  70     enum Status
  71     {
  72         /// Initialized but not running yet.  All CPUs start in
  73         /// this state, but most transition to Active on cycle 1.
  74         /// In MP or SMT systems, non-primary contexts will stay
  75         /// in this state until a thread is assigned to them.
  76         Unallocated,
  77
  78         /// Running.  Instructions should be executed only when
  79         /// the context is in this state.
  80         Active,
  81
  82         /// Temporarily inactive.  Entered while waiting for
  83         /// initialization,synchronization, etc.
  84         Suspended,
  85
  86         /// Permanently shut down.  Entered when target executes
  87         /// m5exit pseudo-instruction.  When all contexts enter
  88         /// this state, the simulation will terminate.
  89         Halted
  90     };
  91
  92   private:
  93     Status _status;
  94
  95   public:
  96     Status status() const { return _status; }
  97
  98     void setStatus(Status newStatus) { _status = newStatus; }
  99
 100     /// Set the status to Active.  Optional delay indicates number of
 101     /// cycles to wait before beginning execution.
 102     void activate(int delay = 1);
 103
 104     /// Set the status to Suspended.
 105     void suspend();
 106
 107     /// Set the status to Unallocated.
 108     void deallocate();
 109
 110     /// Set the status to Halted.
 111     void halt();
 112
 113   public:
 114     RegFile regs;       // correct-path register context
 115
 116     // pointer to CPU associated with this context
 117     BaseCPU *cpu;
 118
 119     // Current instruction
 120     MachInst inst;
 121
 122     // Index of hardware thread context on the CPU that this represents.
 123     int thread_num;
 124
 125     // ID of this context w.r.t. the System or Process object to which
 126     // it belongs.  For full-system mode, this is the system CPU ID.
 127     int cpu_id;
 128
 129 #if FULL_SYSTEM
 130     FunctionalMemory *mem;
 131     AlphaITB *itb;
 132     AlphaDTB *dtb;
 133     System *system;
 134
 135     // the following two fields are redundant, since we can always
 136     // look them up through the system pointer, but we'll leave them
 137     // here for now for convenience
 138     MemoryController *memctrl;
 139     PhysicalMemory *physmem;
 140
 141     Kernel::Binning *kernelBinning;
 142     Kernel::Statistics *kernelStats;
 143     bool bin;
 144     bool fnbin;
 145
 146     FunctionProfile *profile;
 147     ProfileNode *profileNode;
 148     Addr profilePC;
 149     void dumpFuncProfile();
 150
 151 #else
 152     Process *process;
 153
 154     FunctionalMemory *mem;      // functional storage for process address space
 155
 156     // Address space ID.  Note that this is used for TIMING cache
 157     // simulation only; all functional memory accesses should use
 158     // one of the FunctionalMemory pointers above.
 159     short asid;
 160
 161 #endif
 162
 163     /**
 164      * Temporary storage to pass the source address from copy_load to
 165      * copy_store.
 166      * @todo Remove this temporary when we have a better way to do it.
 167      */
 168     Addr copySrcAddr;
 169     /**
 170      * Temp storage for the physical source address of a copy.
 171      * @todo Remove this temporary when we have a better way to do it.
 172      */
 173     Addr copySrcPhysAddr;
 174
 175
 176     /*
 177      * number of executed instructions, for matching with syscall trace
 178      * points in EIO files.
 179      */
 180     Counter func_exe_inst;
 181
 182     //
 183     // Count failed store conditionals so we can warn of apparent
 184     // application deadlock situations.
 185     unsigned storeCondFailures;
 186
 187     // constructor: initialize context from given process structure
 188 #if FULL_SYSTEM
 189     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 190                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 191 #else
 192     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 193     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 194                 int _asid);
 195 #endif
 196     virtual ~ExecContext();
 197
 198     virtual void takeOverFrom(ExecContext *oldContext);
 199
 200     void regStats(const std::string &name);
 201
 202     void serialize(std::ostream &os);
 203     void unserialize(Checkpoint *cp, const std::string &section);
 204
 205 #if FULL_SYSTEM
 206     bool validInstAddr(Addr addr) { return true; }
 207     bool validDataAddr(Addr addr) { return true; }
 208     int getInstAsid() { return regs.instAsid(); }
 209     int getDataAsid() { return regs.dataAsid(); }
 210
 211     Fault translateInstReq(MemReqPtr &req)
 212     {
 213         return itb->translate(req);
 214     }
 215
 216     Fault translateDataReadReq(MemReqPtr &req)
 217     {
 218         return dtb->translate(req, false);
 219     }
 220
 221     Fault translateDataWriteReq(MemReqPtr &req)
 222     {
 223         return dtb->translate(req, true);
 224     }
 225
 226 #else
 227     bool validInstAddr(Addr addr)
 228     { return process->validInstAddr(addr); }
 229
 230     bool validDataAddr(Addr addr)
 231     { return process->validDataAddr(addr); }
 232
 233     int getInstAsid() { return asid; }
 234     int getDataAsid() { return asid; }
 235
 236     Fault dummyTranslation(MemReqPtr &req)
 237     {
 238 #if 0
 239         assert((req->vaddr >> 48 & 0xffff) == 0);
 240 #endif
 241
 242         // put the asid in the upper 16 bits of the paddr
 243         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 244         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 245         return No_Fault;
 246     }
 247     Fault translateInstReq(MemReqPtr &req)
 248     {
 249         return dummyTranslation(req);
 250     }
 251     Fault translateDataReadReq(MemReqPtr &req)
 252     {
 253         return dummyTranslation(req);
 254     }
 255     Fault translateDataWriteReq(MemReqPtr &req)
 256     {
 257         return dummyTranslation(req);
 258     }
 259
 260 #endif
 261
 262     template <class T>
 263     Fault read(MemReqPtr &req, T &data)
 264     {
 265 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 266         if (req->flags & LOCKED) {
 267             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 268             cregs->lock_addr = req->paddr;
 269             cregs->lock_flag = true;
 270         }
 271 #endif
 272
 273         Fault error;
 274         error = mem->read(req, data);
 275         data = LittleEndianGuest::gtoh(data);
 276         return error;
 277     }
 278
 279     template <class T>
 280     Fault write(MemReqPtr &req, T &data)
 281     {
 282 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 283
 284         MiscRegFile *cregs;
 285
 286         // If this is a store conditional, act appropriately
 287         if (req->flags & LOCKED) {
 288             cregs = &req->xc->regs.miscRegs;
 289
 290             if (req->flags & UNCACHEABLE) {
 291                 // Don't update result register (see stq_c in isa_desc)
 292                 req->result = 2;
 293                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 294             } else {
 295                 req->result = cregs->lock_flag;
 296                 if (!cregs->lock_flag ||
 297                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 298                     cregs->lock_flag = false;
 299                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 300                         std::cerr << "Warning: "
 301                                   << req->xc->storeCondFailures
 302                                   << " consecutive store conditional failures "
 303                                   << "on cpu " << req->xc->cpu_id
 304                                   << std::endl;
 305                     }
 306                     return No_Fault;
 307                 }
 308                 else req->xc->storeCondFailures = 0;
 309             }
 310         }
 311
 312         // Need to clear any locked flags on other proccessors for
 313         // this address.  Only do this for succsful Store Conditionals
 314         // and all other stores (WH64?).  Unsuccessful Store
 315         // Conditionals would have returned above, and wouldn't fall
 316         // through.
 317         for (int i = 0; i < system->execContexts.size(); i++){
 318             cregs = &system->execContexts[i]->regs.miscRegs;
 319             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 320                 cregs->lock_flag = false;
 321             }
 322         }
 323
 324 #endif
 325         return mem->write(req, (T)LittleEndianGuest::htog(data));
 326     }
 327
 328     virtual bool misspeculating();
 329
 330
 331     MachInst getInst() { return inst; }
 332
 333     void setInst(MachInst new_inst)
 334     {
 335         inst = new_inst;
 336     }
 337
 338     Fault instRead(MemReqPtr &req)
 339     {
 340         return mem->read(req, inst);
 341     }
 342
 343     //
 344     // New accessors for new decoder.
 345     //
 346     uint64_t readIntReg(int reg_idx)
 347     {
 348         return regs.intRegFile[reg_idx];
 349     }
 350
 351     float readFloatRegSingle(int reg_idx)
 352     {
 353         return (float)regs.floatRegFile.d[reg_idx];
 354     }
 355
 356     double readFloatRegDouble(int reg_idx)
 357     {
 358         return regs.floatRegFile.d[reg_idx];
 359     }
 360
 361     uint64_t readFloatRegInt(int reg_idx)
 362     {
 363         return regs.floatRegFile.q[reg_idx];
 364     }
 365
 366     void setIntReg(int reg_idx, uint64_t val)
 367     {
 368         regs.intRegFile[reg_idx] = val;
 369     }
 370
 371     void setFloatRegSingle(int reg_idx, float val)
 372     {
 373         regs.floatRegFile.d[reg_idx] = (double)val;
 374     }
 375
 376     void setFloatRegDouble(int reg_idx, double val)
 377     {
 378         regs.floatRegFile.d[reg_idx] = val;
 379     }
 380
 381     void setFloatRegInt(int reg_idx, uint64_t val)
 382     {
 383         regs.floatRegFile.q[reg_idx] = val;
 384     }
 385
 386     uint64_t readPC()
 387     {
 388         return regs.pc;
 389     }
 390
 391     void setNextPC(uint64_t val)
 392     {
 393         regs.npc = val;
 394     }
 395
 396     uint64_t readUniq()
 397     {
 398         return regs.miscRegs.uniq;
 399     }
 400
 401     void setUniq(uint64_t val)
 402     {
 403         regs.miscRegs.uniq = val;
 404     }
 405
 406     uint64_t readFpcr()
 407     {
 408         return regs.miscRegs.fpcr;
 409     }
 410
 411     void setFpcr(uint64_t val)
 412     {
 413         regs.miscRegs.fpcr = val;
 414     }
 415
 416 #if FULL_SYSTEM
 417     uint64_t readIpr(int idx, Fault &fault);
 418     Fault setIpr(int idx, uint64_t val);
 419     int readIntrFlag() { return regs.intrflag; }
 420     void setIntrFlag(int val) { regs.intrflag = val; }
 421     Fault hwrei();
 422     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
 423     void ev5_trap(Fault fault);
 424     bool simPalCheck(int palFunc);
 425 #endif
 426
 427     /** Meant to be more generic trap function to be
 428      *  called when an instruction faults.
 429      *  @param fault The fault generated by executing the instruction.
 430      *  @todo How to do this properly so it's dependent upon ISA only?
 431      */
 432
 433     void trap(Fault fault);
 434
 435 #if !FULL_SYSTEM
 436     IntReg getSyscallArg(int i)
 437     {
 438         return regs.intRegFile[ArgumentReg0 + i];
 439     }
 440
 441     // used to shift args for indirect syscall
 442     void setSyscallArg(int i, IntReg val)
 443     {
 444         regs.intRegFile[ArgumentReg0 + i] = val;
 445     }
 446
 447     void setSyscallReturn(SyscallReturn return_value)
 448     {
 449         // check for error condition.  Alpha syscall convention is to
 450         // indicate success/failure in reg a3 (r19) and put the
 451         // return value itself in the standard return value reg (v0).
 452         const int RegA3 = 19;   // only place this is used
 453         if (return_value.successful()) {
 454             // no error
 455             regs.intRegFile[RegA3] = 0;
 456             regs.intRegFile[ReturnValueReg] = return_value.value();
 457         } else {
 458             // got an error, return details
 459             regs.intRegFile[RegA3] = (IntReg) -1;
 460             regs.intRegFile[ReturnValueReg] = -return_value.value();
 461         }
 462     }
 463
 464     void syscall()
 465     {
 466         process->syscall(this);
 467     }
 468 #endif
 469 };
 470
 471
 472 // for non-speculative execution context, spec_mode is always false
 473 inline bool
 474 ExecContext::misspeculating()
 475 {
 476     return false;
 477 }
 478
 479 #endif // __CPU_EXEC_CONTEXT_HH__