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29 #ifndef __CPU_EXEC_CONTEXT_HH__
30 #define __CPU_EXEC_CONTEXT_HH__
32 #include "config/full_system.hh"
33 #include "mem/functional/functional.hh"
34 #include "mem/mem_req.hh"
35 #include "sim/host.hh"
36 #include "sim/serialize.hh"
37 #include "arch/isa_traits.hh"
38 //#include "arch/isa_registers.hh"
39 #include "sim/byteswap.hh"
41 // forward declaration: see functional_memory.hh
42 class FunctionalMemory;
48 #include "sim/system.hh"
49 #include "targetarch/alpha_memory.hh"
51 class FunctionProfile;
53 class MemoryController;
54 namespace Kernel { class Binning; class Statistics; }
58 #include "sim/process.hh"
63 // The ExecContext object represents a functional context for
64 // instruction execution. It incorporates everything required for
65 // architecture-level functional simulation of a single thread.
71 typedef TheISA::RegFile RegFile;
72 typedef TheISA::MachInst MachInst;
73 typedef TheISA::MiscRegFile MiscRegFile;
77 /// Initialized but not running yet. All CPUs start in
78 /// this state, but most transition to Active on cycle 1.
79 /// In MP or SMT systems, non-primary contexts will stay
80 /// in this state until a thread is assigned to them.
83 /// Running. Instructions should be executed only when
84 /// the context is in this state.
87 /// Temporarily inactive. Entered while waiting for
88 /// initialization,synchronization, etc.
91 /// Permanently shut down. Entered when target executes
92 /// m5exit pseudo-instruction. When all contexts enter
93 /// this state, the simulation will terminate.
101 Status status() const { return _status; }
103 void setStatus(Status newStatus) { _status = newStatus; }
105 /// Set the status to Active. Optional delay indicates number of
106 /// cycles to wait before beginning execution.
107 void activate(int delay = 1);
109 /// Set the status to Suspended.
112 /// Set the status to Unallocated.
115 /// Set the status to Halted.
119 RegFile regs; // correct-path register context
121 // pointer to CPU associated with this context
124 // Current instruction
127 // Index of hardware thread context on the CPU that this represents.
130 // ID of this context w.r.t. the System or Process object to which
131 // it belongs. For full-system mode, this is the system CPU ID.
135 FunctionalMemory *mem;
140 // the following two fields are redundant, since we can always
141 // look them up through the system pointer, but we'll leave them
142 // here for now for convenience
143 MemoryController *memctrl;
144 PhysicalMemory *physmem;
146 Kernel::Binning *kernelBinning;
147 Kernel::Statistics *kernelStats;
151 FunctionProfile *profile;
152 ProfileNode *profileNode;
154 void dumpFuncProfile();
159 FunctionalMemory *mem; // functional storage for process address space
161 // Address space ID. Note that this is used for TIMING cache
162 // simulation only; all functional memory accesses should use
163 // one of the FunctionalMemory pointers above.
169 * Temporary storage to pass the source address from copy_load to
171 * @todo Remove this temporary when we have a better way to do it.
175 * Temp storage for the physical source address of a copy.
176 * @todo Remove this temporary when we have a better way to do it.
178 Addr copySrcPhysAddr;
182 * number of executed instructions, for matching with syscall trace
183 * points in EIO files.
185 Counter func_exe_inst;
188 // Count failed store conditionals so we can warn of apparent
189 // application deadlock situations.
190 unsigned storeCondFailures;
192 // constructor: initialize context from given process structure
194 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
195 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
197 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
198 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
201 virtual ~ExecContext();
203 virtual void takeOverFrom(ExecContext *oldContext);
205 void regStats(const std::string &name);
207 void serialize(std::ostream &os);
208 void unserialize(Checkpoint *cp, const std::string §ion);
211 bool validInstAddr(Addr addr) { return true; }
212 bool validDataAddr(Addr addr) { return true; }
213 int getInstAsid() { return regs.instAsid(); }
214 int getDataAsid() { return regs.dataAsid(); }
216 Fault translateInstReq(MemReqPtr &req)
218 return itb->translate(req);
221 Fault translateDataReadReq(MemReqPtr &req)
223 return dtb->translate(req, false);
226 Fault translateDataWriteReq(MemReqPtr &req)
228 return dtb->translate(req, true);
232 bool validInstAddr(Addr addr)
233 { return process->validInstAddr(addr); }
235 bool validDataAddr(Addr addr)
236 { return process->validDataAddr(addr); }
238 int getInstAsid() { return asid; }
239 int getDataAsid() { return asid; }
241 Fault dummyTranslation(MemReqPtr &req)
244 assert((req->vaddr >> 48 & 0xffff) == 0);
247 // put the asid in the upper 16 bits of the paddr
248 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
249 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
252 Fault translateInstReq(MemReqPtr &req)
254 return dummyTranslation(req);
256 Fault translateDataReadReq(MemReqPtr &req)
258 return dummyTranslation(req);
260 Fault translateDataWriteReq(MemReqPtr &req)
262 return dummyTranslation(req);
268 Fault read(MemReqPtr &req, T &data)
270 #if FULL_SYSTEM && defined(TARGET_ALPHA)
271 if (req->flags & LOCKED) {
272 MiscRegFile *cregs = &req->xc->regs.miscRegs;
273 cregs->lock_addr = req->paddr;
274 cregs->lock_flag = true;
279 error = mem->read(req, data);
280 data = LittleEndianGuest::gtoh(data);
285 Fault write(MemReqPtr &req, T &data)
287 #if FULL_SYSTEM && defined(TARGET_ALPHA)
291 // If this is a store conditional, act appropriately
292 if (req->flags & LOCKED) {
293 cregs = &req->xc->regs.miscRegs;
295 if (req->flags & UNCACHEABLE) {
296 // Don't update result register (see stq_c in isa_desc)
298 req->xc->storeCondFailures = 0;//Needed? [RGD]
300 req->result = cregs->lock_flag;
301 if (!cregs->lock_flag ||
302 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
303 cregs->lock_flag = false;
304 if (((++req->xc->storeCondFailures) % 100000) == 0) {
305 std::cerr << "Warning: "
306 << req->xc->storeCondFailures
307 << " consecutive store conditional failures "
308 << "on cpu " << req->xc->cpu_id
313 else req->xc->storeCondFailures = 0;
317 // Need to clear any locked flags on other proccessors for
318 // this address. Only do this for succsful Store Conditionals
319 // and all other stores (WH64?). Unsuccessful Store
320 // Conditionals would have returned above, and wouldn't fall
322 for (int i = 0; i < system->execContexts.size(); i++){
323 cregs = &system->execContexts[i]->regs.miscRegs;
324 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
325 cregs->lock_flag = false;
330 return mem->write(req, (T)LittleEndianGuest::htog(data));
333 virtual bool misspeculating();
336 MachInst getInst() { return inst; }
338 void setInst(MachInst new_inst)
343 Fault instRead(MemReqPtr &req)
345 return mem->read(req, inst);
349 // New accessors for new decoder.
351 uint64_t readIntReg(int reg_idx)
353 return regs.intRegFile[reg_idx];
356 float readFloatRegSingle(int reg_idx)
358 return (float)regs.floatRegFile.d[reg_idx];
361 double readFloatRegDouble(int reg_idx)
363 return regs.floatRegFile.d[reg_idx];
366 uint64_t readFloatRegInt(int reg_idx)
368 return regs.floatRegFile.q[reg_idx];
371 void setIntReg(int reg_idx, uint64_t val)
373 regs.intRegFile[reg_idx] = val;
376 void setFloatRegSingle(int reg_idx, float val)
378 regs.floatRegFile.d[reg_idx] = (double)val;
381 void setFloatRegDouble(int reg_idx, double val)
383 regs.floatRegFile.d[reg_idx] = val;
386 void setFloatRegInt(int reg_idx, uint64_t val)
388 regs.floatRegFile.q[reg_idx] = val;
396 void setNextPC(uint64_t val)
403 return regs.miscRegs.uniq;
406 void setUniq(uint64_t val)
408 regs.miscRegs.uniq = val;
413 return regs.miscRegs.fpcr;
416 void setFpcr(uint64_t val)
418 regs.miscRegs.fpcr = val;
422 uint64_t readIpr(int idx, Fault &fault);
423 Fault setIpr(int idx, uint64_t val);
424 int readIntrFlag() { return regs.intrflag; }
425 void setIntrFlag(int val) { regs.intrflag = val; }
427 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
428 void ev5_trap(Fault fault);
429 bool simPalCheck(int palFunc);
432 /** Meant to be more generic trap function to be
433 * called when an instruction faults.
434 * @param fault The fault generated by executing the instruction.
435 * @todo How to do this properly so it's dependent upon ISA only?
438 void trap(Fault fault);
441 TheISA::IntReg getSyscallArg(int i)
443 return regs.intRegFile[TheISA::ArgumentReg0 + i];
446 // used to shift args for indirect syscall
447 void setSyscallArg(int i, TheISA::IntReg val)
449 regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
452 void setSyscallReturn(SyscallReturn return_value)
454 // check for error condition. Alpha syscall convention is to
455 // indicate success/failure in reg a3 (r19) and put the
456 // return value itself in the standard return value reg (v0).
457 const int RegA3 = 19; // only place this is used
458 if (return_value.successful()) {
460 regs.intRegFile[RegA3] = 0;
461 regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
463 // got an error, return details
464 regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
465 regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
471 process->syscall(this);
477 // for non-speculative execution context, spec_mode is always false
479 ExecContext::misspeculating()
484 #endif // __CPU_EXEC_CONTEXT_HH__