cpu/exec_context.hh

   1 /*
   2  * Copyright (c) 2001-2005 The Regents of The University of Michigan
   3  * All rights reserved.
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   5  * Redistribution and use in source and binary forms, with or without
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   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_EXEC_CONTEXT_HH__
  30 #define __CPU_EXEC_CONTEXT_HH__
  31
  32 #include "config/full_system.hh"
  33 #include "mem/functional/functional.hh"
  34 #include "mem/mem_req.hh"
  35 #include "sim/host.hh"
  36 #include "sim/serialize.hh"
  37 #include "arch/isa_traits.hh"
  38 #include "sim/byteswap.hh"
  39
  40 // forward declaration: see functional_memory.hh
  41 class FunctionalMemory;
  42 class PhysicalMemory;
  43 class BaseCPU;
  44
  45 #if FULL_SYSTEM
  46
  47 #include "sim/system.hh"
  48 #include "targetarch/alpha_memory.hh"
  49
  50 class FunctionProfile;
  51 class ProfileNode;
  52 class MemoryController;
  53 namespace Kernel { class Binning; class Statistics; }
  54
  55 #else // !FULL_SYSTEM
  56
  57 #include "sim/process.hh"
  58
  59 #endif // FULL_SYSTEM
  60
  61 //
  62 // The ExecContext object represents a functional context for
  63 // instruction execution.  It incorporates everything required for
  64 // architecture-level functional simulation of a single thread.
  65 //
  66
  67 class ExecContext
  68 {
  69   public:
  70     enum Status
  71     {
  72         /// Initialized but not running yet.  All CPUs start in
  73         /// this state, but most transition to Active on cycle 1.
  74         /// In MP or SMT systems, non-primary contexts will stay
  75         /// in this state until a thread is assigned to them.
  76         Unallocated,
  77
  78         /// Running.  Instructions should be executed only when
  79         /// the context is in this state.
  80         Active,
  81
  82         /// Temporarily inactive.  Entered while waiting for
  83         /// synchronization, etc.
  84         Suspended,
  85
  86         /// Permanently shut down.  Entered when target executes
  87         /// m5exit pseudo-instruction.  When all contexts enter
  88         /// this state, the simulation will terminate.
  89         Halted
  90     };
  91
  92   private:
  93     Status _status;
  94
  95   public:
  96     Status status() const { return _status; }
  97
  98     /// Set the status to Active.  Optional delay indicates number of
  99     /// cycles to wait before beginning execution.
 100     void activate(int delay = 1);
 101
 102     /// Set the status to Suspended.
 103     void suspend();
 104
 105     /// Set the status to Unallocated.
 106     void deallocate();
 107
 108     /// Set the status to Halted.
 109     void halt();
 110
 111   public:
 112     RegFile regs;       // correct-path register context
 113
 114     // pointer to CPU associated with this context
 115     BaseCPU *cpu;
 116
 117     // Current instruction
 118     MachInst inst;
 119
 120     // Index of hardware thread context on the CPU that this represents.
 121     int thread_num;
 122
 123     // ID of this context w.r.t. the System or Process object to which
 124     // it belongs.  For full-system mode, this is the system CPU ID.
 125     int cpu_id;
 126
 127 #if FULL_SYSTEM
 128     FunctionalMemory *mem;
 129     AlphaITB *itb;
 130     AlphaDTB *dtb;
 131     System *system;
 132
 133     // the following two fields are redundant, since we can always
 134     // look them up through the system pointer, but we'll leave them
 135     // here for now for convenience
 136     MemoryController *memctrl;
 137     PhysicalMemory *physmem;
 138
 139     Kernel::Binning *kernelBinning;
 140     Kernel::Statistics *kernelStats;
 141     bool bin;
 142     bool fnbin;
 143
 144     FunctionProfile *profile;
 145     ProfileNode *profileNode;
 146     Addr profilePC;
 147     void dumpFuncProfile();
 148
 149 #else
 150     Process *process;
 151
 152     FunctionalMemory *mem;      // functional storage for process address space
 153
 154     // Address space ID.  Note that this is used for TIMING cache
 155     // simulation only; all functional memory accesses should use
 156     // one of the FunctionalMemory pointers above.
 157     short asid;
 158
 159 #endif
 160
 161     /**
 162      * Temporary storage to pass the source address from copy_load to
 163      * copy_store.
 164      * @todo Remove this temporary when we have a better way to do it.
 165      */
 166     Addr copySrcAddr;
 167     /**
 168      * Temp storage for the physical source address of a copy.
 169      * @todo Remove this temporary when we have a better way to do it.
 170      */
 171     Addr copySrcPhysAddr;
 172
 173
 174     /*
 175      * number of executed instructions, for matching with syscall trace
 176      * points in EIO files.
 177      */
 178     Counter func_exe_inst;
 179
 180     //
 181     // Count failed store conditionals so we can warn of apparent
 182     // application deadlock situations.
 183     unsigned storeCondFailures;
 184
 185     // constructor: initialize context from given process structure
 186 #if FULL_SYSTEM
 187     ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
 188                 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
 189 #else
 190     ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
 191     ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
 192                 int _asid);
 193 #endif
 194     virtual ~ExecContext();
 195
 196     virtual void takeOverFrom(ExecContext *oldContext);
 197
 198     void regStats(const std::string &name);
 199
 200     void serialize(std::ostream &os);
 201     void unserialize(Checkpoint *cp, const std::string &section);
 202
 203 #if FULL_SYSTEM
 204     bool validInstAddr(Addr addr) { return true; }
 205     bool validDataAddr(Addr addr) { return true; }
 206     int getInstAsid() { return regs.instAsid(); }
 207     int getDataAsid() { return regs.dataAsid(); }
 208
 209     Fault * translateInstReq(MemReqPtr &req)
 210     {
 211         return itb->translate(req);
 212     }
 213
 214     Fault * translateDataReadReq(MemReqPtr &req)
 215     {
 216         return dtb->translate(req, false);
 217     }
 218
 219     Fault * translateDataWriteReq(MemReqPtr &req)
 220     {
 221         return dtb->translate(req, true);
 222     }
 223
 224 #else
 225     bool validInstAddr(Addr addr)
 226     { return process->validInstAddr(addr); }
 227
 228     bool validDataAddr(Addr addr)
 229     { return process->validDataAddr(addr); }
 230
 231     int getInstAsid() { return asid; }
 232     int getDataAsid() { return asid; }
 233
 234     Fault * dummyTranslation(MemReqPtr &req)
 235     {
 236 #if 0
 237         assert((req->vaddr >> 48 & 0xffff) == 0);
 238 #endif
 239
 240         // put the asid in the upper 16 bits of the paddr
 241         req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
 242         req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
 243         return NoFault;
 244     }
 245     Fault * translateInstReq(MemReqPtr &req)
 246     {
 247         return dummyTranslation(req);
 248     }
 249     Fault * translateDataReadReq(MemReqPtr &req)
 250     {
 251         return dummyTranslation(req);
 252     }
 253     Fault * translateDataWriteReq(MemReqPtr &req)
 254     {
 255         return dummyTranslation(req);
 256     }
 257
 258 #endif
 259
 260     template <class T>
 261     Fault * read(MemReqPtr &req, T &data)
 262     {
 263 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 264         if (req->flags & LOCKED) {
 265             MiscRegFile *cregs = &req->xc->regs.miscRegs;
 266             cregs->lock_addr = req->paddr;
 267             cregs->lock_flag = true;
 268         }
 269 #endif
 270
 271         Fault * error;
 272         error = mem->read(req, data);
 273         data = LittleEndianGuest::gtoh(data);
 274         return error;
 275     }
 276
 277     template <class T>
 278     Fault * write(MemReqPtr &req, T &data)
 279     {
 280 #if FULL_SYSTEM && defined(TARGET_ALPHA)
 281
 282         MiscRegFile *cregs;
 283
 284         // If this is a store conditional, act appropriately
 285         if (req->flags & LOCKED) {
 286             cregs = &req->xc->regs.miscRegs;
 287
 288             if (req->flags & UNCACHEABLE) {
 289                 // Don't update result register (see stq_c in isa_desc)
 290                 req->result = 2;
 291                 req->xc->storeCondFailures = 0;//Needed? [RGD]
 292             } else {
 293                 req->result = cregs->lock_flag;
 294                 if (!cregs->lock_flag ||
 295                     ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
 296                     cregs->lock_flag = false;
 297                     if (((++req->xc->storeCondFailures) % 100000) == 0) {
 298                         std::cerr << "Warning: "
 299                                   << req->xc->storeCondFailures
 300                                   << " consecutive store conditional failures "
 301                                   << "on cpu " << req->xc->cpu_id
 302                                   << std::endl;
 303                     }
 304                     return NoFault;
 305                 }
 306                 else req->xc->storeCondFailures = 0;
 307             }
 308         }
 309
 310         // Need to clear any locked flags on other proccessors for
 311         // this address.  Only do this for succsful Store Conditionals
 312         // and all other stores (WH64?).  Unsuccessful Store
 313         // Conditionals would have returned above, and wouldn't fall
 314         // through.
 315         for (int i = 0; i < system->execContexts.size(); i++){
 316             cregs = &system->execContexts[i]->regs.miscRegs;
 317             if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
 318                 cregs->lock_flag = false;
 319             }
 320         }
 321
 322 #endif
 323         return mem->write(req, (T)LittleEndianGuest::htog(data));
 324     }
 325
 326     virtual bool misspeculating();
 327
 328
 329     MachInst getInst() { return inst; }
 330
 331     void setInst(MachInst new_inst)
 332     {
 333         inst = new_inst;
 334     }
 335
 336     Fault * instRead(MemReqPtr &req)
 337     {
 338         return mem->read(req, inst);
 339     }
 340
 341     //
 342     // New accessors for new decoder.
 343     //
 344     uint64_t readIntReg(int reg_idx)
 345     {
 346         return regs.intRegFile[reg_idx];
 347     }
 348
 349     float readFloatRegSingle(int reg_idx)
 350     {
 351         return (float)regs.floatRegFile.d[reg_idx];
 352     }
 353
 354     double readFloatRegDouble(int reg_idx)
 355     {
 356         return regs.floatRegFile.d[reg_idx];
 357     }
 358
 359     uint64_t readFloatRegInt(int reg_idx)
 360     {
 361         return regs.floatRegFile.q[reg_idx];
 362     }
 363
 364     void setIntReg(int reg_idx, uint64_t val)
 365     {
 366         regs.intRegFile[reg_idx] = val;
 367     }
 368
 369     void setFloatRegSingle(int reg_idx, float val)
 370     {
 371         regs.floatRegFile.d[reg_idx] = (double)val;
 372     }
 373
 374     void setFloatRegDouble(int reg_idx, double val)
 375     {
 376         regs.floatRegFile.d[reg_idx] = val;
 377     }
 378
 379     void setFloatRegInt(int reg_idx, uint64_t val)
 380     {
 381         regs.floatRegFile.q[reg_idx] = val;
 382     }
 383
 384     uint64_t readPC()
 385     {
 386         return regs.pc;
 387     }
 388
 389     void setNextPC(uint64_t val)
 390     {
 391         regs.npc = val;
 392     }
 393
 394     uint64_t readUniq()
 395     {
 396         return regs.miscRegs.uniq;
 397     }
 398
 399     void setUniq(uint64_t val)
 400     {
 401         regs.miscRegs.uniq = val;
 402     }
 403
 404     uint64_t readFpcr()
 405     {
 406         return regs.miscRegs.fpcr;
 407     }
 408
 409     void setFpcr(uint64_t val)
 410     {
 411         regs.miscRegs.fpcr = val;
 412     }
 413
 414 #if FULL_SYSTEM
 415     uint64_t readIpr(int idx, Fault * &fault);
 416     Fault * setIpr(int idx, uint64_t val);
 417     int readIntrFlag() { return regs.intrflag; }
 418     void setIntrFlag(int val) { regs.intrflag = val; }
 419     Fault * hwrei();
 420     bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
 421     void ev5_trap(Fault * fault);
 422     bool simPalCheck(int palFunc);
 423 #endif
 424
 425     /** Meant to be more generic trap function to be
 426      *  called when an instruction faults.
 427      *  @param fault The fault generated by executing the instruction.
 428      *  @todo How to do this properly so it's dependent upon ISA only?
 429      */
 430
 431     void trap(Fault * fault);
 432
 433 #if !FULL_SYSTEM
 434     IntReg getSyscallArg(int i)
 435     {
 436         return regs.intRegFile[ArgumentReg0 + i];
 437     }
 438
 439     // used to shift args for indirect syscall
 440     void setSyscallArg(int i, IntReg val)
 441     {
 442         regs.intRegFile[ArgumentReg0 + i] = val;
 443     }
 444
 445     void setSyscallReturn(SyscallReturn return_value)
 446     {
 447         // check for error condition.  Alpha syscall convention is to
 448         // indicate success/failure in reg a3 (r19) and put the
 449         // return value itself in the standard return value reg (v0).
 450         const int RegA3 = 19;   // only place this is used
 451         if (return_value.successful()) {
 452             // no error
 453             regs.intRegFile[RegA3] = 0;
 454             regs.intRegFile[ReturnValueReg] = return_value.value();
 455         } else {
 456             // got an error, return details
 457             regs.intRegFile[RegA3] = (IntReg) -1;
 458             regs.intRegFile[ReturnValueReg] = -return_value.value();
 459         }
 460     }
 461
 462     void syscall()
 463     {
 464         process->syscall(this);
 465     }
 466 #endif
 467 };
 468
 469
 470 // for non-speculative execution context, spec_mode is always false
 471 inline bool
 472 ExecContext::misspeculating()
 473 {
 474     return false;
 475 }
 476
 477 #endif // __CPU_EXEC_CONTEXT_HH__