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29 #ifndef __CPU_EXEC_CONTEXT_HH__
30 #define __CPU_EXEC_CONTEXT_HH__
32 #include "config/full_system.hh"
33 #include "mem/functional/functional.hh"
34 #include "mem/mem_req.hh"
35 #include "sim/host.hh"
36 #include "sim/serialize.hh"
37 #include "arch/isa_traits.hh"
38 //#include "arch/isa_registers.hh"
39 #include "sim/byteswap.hh"
41 // forward declaration: see functional_memory.hh
42 class FunctionalMemory;
48 #include "sim/system.hh"
49 #include "targetarch/alpha_memory.hh"
51 class FunctionProfile;
53 class MemoryController;
54 namespace Kernel { class Binning; class Statistics; }
58 #include "sim/process.hh"
63 // The ExecContext object represents a functional context for
64 // instruction execution. It incorporates everything required for
65 // architecture-level functional simulation of a single thread.
71 typedef TheISA::RegFile RegFile;
72 typedef TheISA::Addr Addr;
73 typedef TheISA::MachInst MachInst;
74 typedef TheISA::MiscRegFile MiscRegFile;
78 /// Initialized but not running yet. All CPUs start in
79 /// this state, but most transition to Active on cycle 1.
80 /// In MP or SMT systems, non-primary contexts will stay
81 /// in this state until a thread is assigned to them.
84 /// Running. Instructions should be executed only when
85 /// the context is in this state.
88 /// Temporarily inactive. Entered while waiting for
89 /// initialization,synchronization, etc.
92 /// Permanently shut down. Entered when target executes
93 /// m5exit pseudo-instruction. When all contexts enter
94 /// this state, the simulation will terminate.
102 Status status() const { return _status; }
104 void setStatus(Status newStatus) { _status = newStatus; }
106 /// Set the status to Active. Optional delay indicates number of
107 /// cycles to wait before beginning execution.
108 void activate(int delay = 1);
110 /// Set the status to Suspended.
113 /// Set the status to Unallocated.
116 /// Set the status to Halted.
120 RegFile regs; // correct-path register context
122 // pointer to CPU associated with this context
125 // Current instruction
128 // Index of hardware thread context on the CPU that this represents.
131 // ID of this context w.r.t. the System or Process object to which
132 // it belongs. For full-system mode, this is the system CPU ID.
136 FunctionalMemory *mem;
141 // the following two fields are redundant, since we can always
142 // look them up through the system pointer, but we'll leave them
143 // here for now for convenience
144 MemoryController *memctrl;
145 PhysicalMemory *physmem;
147 Kernel::Binning *kernelBinning;
148 Kernel::Statistics *kernelStats;
152 FunctionProfile *profile;
153 ProfileNode *profileNode;
155 void dumpFuncProfile();
160 FunctionalMemory *mem; // functional storage for process address space
162 // Address space ID. Note that this is used for TIMING cache
163 // simulation only; all functional memory accesses should use
164 // one of the FunctionalMemory pointers above.
170 * Temporary storage to pass the source address from copy_load to
172 * @todo Remove this temporary when we have a better way to do it.
176 * Temp storage for the physical source address of a copy.
177 * @todo Remove this temporary when we have a better way to do it.
179 Addr copySrcPhysAddr;
183 * number of executed instructions, for matching with syscall trace
184 * points in EIO files.
186 Counter func_exe_inst;
189 // Count failed store conditionals so we can warn of apparent
190 // application deadlock situations.
191 unsigned storeCondFailures;
193 // constructor: initialize context from given process structure
195 ExecContext(BaseCPU *_cpu, int _thread_num, System *_system,
196 AlphaITB *_itb, AlphaDTB *_dtb, FunctionalMemory *_dem);
198 ExecContext(BaseCPU *_cpu, int _thread_num, Process *_process, int _asid);
199 ExecContext(BaseCPU *_cpu, int _thread_num, FunctionalMemory *_mem,
202 virtual ~ExecContext();
204 virtual void takeOverFrom(ExecContext *oldContext);
206 void regStats(const std::string &name);
208 void serialize(std::ostream &os);
209 void unserialize(Checkpoint *cp, const std::string §ion);
212 bool validInstAddr(Addr addr) { return true; }
213 bool validDataAddr(Addr addr) { return true; }
214 int getInstAsid() { return regs.instAsid(); }
215 int getDataAsid() { return regs.dataAsid(); }
217 Fault * translateInstReq(MemReqPtr &req)
219 return itb->translate(req);
222 Fault * translateDataReadReq(MemReqPtr &req)
224 return dtb->translate(req, false);
227 Fault * translateDataWriteReq(MemReqPtr &req)
229 return dtb->translate(req, true);
233 bool validInstAddr(Addr addr)
234 { return process->validInstAddr(addr); }
236 bool validDataAddr(Addr addr)
237 { return process->validDataAddr(addr); }
239 int getInstAsid() { return asid; }
240 int getDataAsid() { return asid; }
242 Fault * dummyTranslation(MemReqPtr &req)
245 assert((req->vaddr >> 48 & 0xffff) == 0);
248 // put the asid in the upper 16 bits of the paddr
249 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
250 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
253 Fault * translateInstReq(MemReqPtr &req)
255 return dummyTranslation(req);
257 Fault * translateDataReadReq(MemReqPtr &req)
259 return dummyTranslation(req);
261 Fault * translateDataWriteReq(MemReqPtr &req)
263 return dummyTranslation(req);
269 Fault * read(MemReqPtr &req, T &data)
271 #if FULL_SYSTEM && defined(TARGET_ALPHA)
272 if (req->flags & LOCKED) {
273 MiscRegFile *cregs = &req->xc->regs.miscRegs;
274 cregs->lock_addr = req->paddr;
275 cregs->lock_flag = true;
280 error = mem->read(req, data);
281 data = LittleEndianGuest::gtoh(data);
286 Fault * write(MemReqPtr &req, T &data)
288 #if FULL_SYSTEM && defined(TARGET_ALPHA)
292 // If this is a store conditional, act appropriately
293 if (req->flags & LOCKED) {
294 cregs = &req->xc->regs.miscRegs;
296 if (req->flags & UNCACHEABLE) {
297 // Don't update result register (see stq_c in isa_desc)
299 req->xc->storeCondFailures = 0;//Needed? [RGD]
301 req->result = cregs->lock_flag;
302 if (!cregs->lock_flag ||
303 ((cregs->lock_addr & ~0xf) != (req->paddr & ~0xf))) {
304 cregs->lock_flag = false;
305 if (((++req->xc->storeCondFailures) % 100000) == 0) {
306 std::cerr << "Warning: "
307 << req->xc->storeCondFailures
308 << " consecutive store conditional failures "
309 << "on cpu " << req->xc->cpu_id
314 else req->xc->storeCondFailures = 0;
318 // Need to clear any locked flags on other proccessors for
319 // this address. Only do this for succsful Store Conditionals
320 // and all other stores (WH64?). Unsuccessful Store
321 // Conditionals would have returned above, and wouldn't fall
323 for (int i = 0; i < system->execContexts.size(); i++){
324 cregs = &system->execContexts[i]->regs.miscRegs;
325 if ((cregs->lock_addr & ~0xf) == (req->paddr & ~0xf)) {
326 cregs->lock_flag = false;
331 return mem->write(req, (T)LittleEndianGuest::htog(data));
334 virtual bool misspeculating();
337 MachInst getInst() { return inst; }
339 void setInst(MachInst new_inst)
344 Fault * instRead(MemReqPtr &req)
346 return mem->read(req, inst);
350 // New accessors for new decoder.
352 uint64_t readIntReg(int reg_idx)
354 return regs.intRegFile[reg_idx];
357 float readFloatRegSingle(int reg_idx)
359 return (float)regs.floatRegFile.d[reg_idx];
362 double readFloatRegDouble(int reg_idx)
364 return regs.floatRegFile.d[reg_idx];
367 uint64_t readFloatRegInt(int reg_idx)
369 return regs.floatRegFile.q[reg_idx];
372 void setIntReg(int reg_idx, uint64_t val)
374 regs.intRegFile[reg_idx] = val;
377 void setFloatRegSingle(int reg_idx, float val)
379 regs.floatRegFile.d[reg_idx] = (double)val;
382 void setFloatRegDouble(int reg_idx, double val)
384 regs.floatRegFile.d[reg_idx] = val;
387 void setFloatRegInt(int reg_idx, uint64_t val)
389 regs.floatRegFile.q[reg_idx] = val;
397 void setNextPC(uint64_t val)
404 return regs.miscRegs.uniq;
407 void setUniq(uint64_t val)
409 regs.miscRegs.uniq = val;
414 return regs.miscRegs.fpcr;
417 void setFpcr(uint64_t val)
419 regs.miscRegs.fpcr = val;
423 uint64_t readIpr(int idx, Fault * &fault);
424 Fault * setIpr(int idx, uint64_t val);
425 int readIntrFlag() { return regs.intrflag; }
426 void setIntrFlag(int val) { regs.intrflag = val; }
428 bool inPalMode() { return AlphaISA::PcPAL(regs.pc); }
429 void ev5_trap(Fault * fault);
430 bool simPalCheck(int palFunc);
433 /** Meant to be more generic trap function to be
434 * called when an instruction faults.
435 * @param fault The fault generated by executing the instruction.
436 * @todo How to do this properly so it's dependent upon ISA only?
439 void trap(Fault * fault);
442 TheISA::IntReg getSyscallArg(int i)
444 return regs.intRegFile[TheISA::ArgumentReg0 + i];
447 // used to shift args for indirect syscall
448 void setSyscallArg(int i, TheISA::IntReg val)
450 regs.intRegFile[TheISA::ArgumentReg0 + i] = val;
453 void setSyscallReturn(SyscallReturn return_value)
455 // check for error condition. Alpha syscall convention is to
456 // indicate success/failure in reg a3 (r19) and put the
457 // return value itself in the standard return value reg (v0).
458 const int RegA3 = 19; // only place this is used
459 if (return_value.successful()) {
461 regs.intRegFile[RegA3] = 0;
462 regs.intRegFile[TheISA::ReturnValueReg] = return_value.value();
464 // got an error, return details
465 regs.intRegFile[RegA3] = (TheISA::IntReg) -1;
466 regs.intRegFile[TheISA::ReturnValueReg] = -return_value.value();
472 process->syscall(this);
478 // for non-speculative execution context, spec_mode is always false
480 ExecContext::misspeculating()
485 #endif // __CPU_EXEC_CONTEXT_HH__