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29 #ifndef __EXETRACE_HH__
30 #define __EXETRACE_HH__
35 #include "sim/host.hh"
36 #include "cpu/inst_seq.hh" // for InstSeqNum
37 #include "base/trace.hh"
38 #include "cpu/exec_context.hh"
39 #include "cpu/static_inst.hh"
46 class InstRecord : public Record
50 // The following fields are initialized by the constructor and
51 // thus guaranteed to be valid.
53 // need to make this ref-counted so it doesn't go away before we
55 StaticInstPtr<TheISA> staticInst;
60 // The remaining fields are only valid for particular instruction
61 // types (e.g, addresses for memory ops) or when particular
62 // options are enabled (e.g., tracing full register contents).
63 // Each data field has an associated valid flag to indicate
64 // whether the data field is valid.
74 DataInt8 = 1, // set to equal number of bytes
94 InstRecord(Tick _cycle, BaseCPU *_cpu,
95 const StaticInstPtr<TheISA> &_staticInst,
96 Addr _pc, bool spec, int _thread)
97 : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
98 misspeculating(spec), thread(_thread)
100 data_status = DataInvalid;
104 fetch_seq_valid = false;
105 cp_seq_valid = false;
108 virtual ~InstRecord() { }
110 virtual void dump(std::ostream &outs);
112 void setAddr(Addr a) { addr = a; addr_valid = true; }
114 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
115 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
116 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
117 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
119 void setData(int64_t d) { setData((uint64_t)d); }
120 void setData(int32_t d) { setData((uint32_t)d); }
121 void setData(int16_t d) { setData((uint16_t)d); }
122 void setData(int8_t d) { setData((uint8_t)d); }
124 void setData(double d) { data.as_double = d; data_status = DataDouble; }
126 void setFetchSeq(InstSeqNum seq)
127 { fetch_seq = seq; fetch_seq_valid = true; }
129 void setCPSeq(InstSeqNum seq)
130 { cp_seq = seq; cp_seq_valid = true; }
132 void setRegs(const IntRegFile ®s);
134 void finalize() { theLog.append(this); }
136 enum InstExecFlagBits {
150 static std::vector<bool> flags;
151 static std::string trace_system;
153 static void setParams();
155 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
160 InstRecord::setRegs(const IntRegFile ®s)
163 iregs = new iRegFile;
165 memcpy(&iregs->regs, regs, sizeof(IntRegFile));
171 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
172 const StaticInstPtr<TheISA> staticInst,
173 Addr pc, int thread = 0)
175 if (DTRACE(InstExec) &&
176 (InstRecord::traceMisspec() || !xc->misspeculating())) {
177 return new InstRecord(cycle, cpu, staticInst, pc,
178 xc->misspeculating(), thread);
187 #endif // __EXETRACE_HH__