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29 #ifndef __EXETRACE_HH__
30 #define __EXETRACE_HH__
35 #include "sim/host.hh"
36 #include "cpu/inst_seq.hh" // for InstSeqNum
37 #include "base/trace.hh"
38 #include "cpu/exec_context.hh"
39 #include "cpu/static_inst.hh"
46 class InstRecord : public Record
49 typedef TheISA::IntRegFile IntRegFile;
51 // The following fields are initialized by the constructor and
52 // thus guaranteed to be valid.
54 // need to make this ref-counted so it doesn't go away before we
56 StaticInstPtr staticInst;
61 // The remaining fields are only valid for particular instruction
62 // types (e.g, addresses for memory ops) or when particular
63 // options are enabled (e.g., tracing full register contents).
64 // Each data field has an associated valid flag to indicate
65 // whether the data field is valid.
75 DataInt8 = 1, // set to equal number of bytes
95 InstRecord(Tick _cycle, BaseCPU *_cpu,
96 const StaticInstPtr &_staticInst,
97 Addr _pc, bool spec, int _thread)
98 : Record(_cycle), cpu(_cpu), staticInst(_staticInst), PC(_pc),
99 misspeculating(spec), thread(_thread)
101 data_status = DataInvalid;
105 fetch_seq_valid = false;
106 cp_seq_valid = false;
109 virtual ~InstRecord() { }
111 virtual void dump(std::ostream &outs);
113 void setAddr(Addr a) { addr = a; addr_valid = true; }
115 void setData(uint64_t d) { data.as_int = d; data_status = DataInt64; }
116 void setData(uint32_t d) { data.as_int = d; data_status = DataInt32; }
117 void setData(uint16_t d) { data.as_int = d; data_status = DataInt16; }
118 void setData(uint8_t d) { data.as_int = d; data_status = DataInt8; }
120 void setData(int64_t d) { setData((uint64_t)d); }
121 void setData(int32_t d) { setData((uint32_t)d); }
122 void setData(int16_t d) { setData((uint16_t)d); }
123 void setData(int8_t d) { setData((uint8_t)d); }
125 void setData(double d) { data.as_double = d; data_status = DataDouble; }
127 void setFetchSeq(InstSeqNum seq)
128 { fetch_seq = seq; fetch_seq_valid = true; }
130 void setCPSeq(InstSeqNum seq)
131 { cp_seq = seq; cp_seq_valid = true; }
133 void setRegs(const IntRegFile ®s);
135 void finalize() { theLog.append(this); }
137 enum InstExecFlagBits {
151 static std::vector<bool> flags;
152 static std::string trace_system;
154 static void setParams();
156 static bool traceMisspec() { return flags[TRACE_MISSPEC]; }
161 InstRecord::setRegs(const IntRegFile ®s)
164 iregs = new iRegFile;
166 memcpy(&iregs->regs, regs, sizeof(IntRegFile));
172 getInstRecord(Tick cycle, ExecContext *xc, BaseCPU *cpu,
173 const StaticInstPtr staticInst,
174 Addr pc, int thread = 0)
176 if (DTRACE(InstExec) &&
177 (InstRecord::traceMisspec() || !xc->misspeculating())) {
178 return new InstRecord(cycle, cpu, staticInst, pc,
179 xc->misspeculating(), thread);
188 #endif // __EXETRACE_HH__