cpu/intr_control.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <string>
  30 #include <vector>
  31
  32 #include "cpu/base_cpu.hh"
  33 #include "cpu/intr_control.hh"
  34 #include "sim/sim_object.hh"
  35
  36 using namespace std;
  37
  38 IntrControl::IntrControl(const string &name, BaseCPU *c)
  39     : SimObject(name), cpu(c)
  40 {}
  41
  42 BEGIN_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
  43
  44     SimObjectParam<BaseCPU *> cpu;
  45
  46 END_DECLARE_SIM_OBJECT_PARAMS(IntrControl)
  47
  48 BEGIN_INIT_SIM_OBJECT_PARAMS(IntrControl)
  49
  50     INIT_PARAM(cpu, "the processor")
  51
  52 END_INIT_SIM_OBJECT_PARAMS(IntrControl)
  53
  54 CREATE_SIM_OBJECT(IntrControl)
  55 {
  56     return new IntrControl(getInstanceName(), cpu);
  57 }
  58
  59 REGISTER_SIM_OBJECT("IntrControl", IntrControl)