cpu/memtest/memtest.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 // FIX ME: make trackBlkAddr use blocksize from actual cache, not hard coded
  30
  31 #include <string>
  32 #include <sstream>
  33 #include <iomanip>
  34 #include <vector>
  35
  36 #include "cpu/memtest/memtest.hh"
  37 #include "base/misc.hh"
  38 #include "sim/sim_events.hh"
  39 #include "mem/functional_mem/main_memory.hh"
  40 #include "mem/cache/base_cache.hh"
  41
  42 #include "base/statistics.hh"
  43 #include "sim/sim_stats.hh"
  44
  45 using namespace std;
  46
  47 MemTest::MemTest(const string &name,
  48                  MemInterface *_cache_interface,
  49                  FunctionalMemory *main_mem,
  50                  FunctionalMemory *check_mem,
  51                  unsigned _memorySize,
  52                  unsigned _percentReads,
  53                  unsigned _percentUncacheable,
  54                  unsigned _progressInterval,
  55                  Addr _traceAddr,
  56                  Counter max_loads_any_thread,
  57                  Counter max_loads_all_threads)
  58     : BaseCPU(name, 1, 0, 0, max_loads_any_thread, max_loads_all_threads),
  59       tickEvent(this),
  60       cacheInterface(_cache_interface),
  61       mainMem(main_mem),
  62       checkMem(check_mem),
  63       size(_memorySize),
  64       percentReads(_percentReads),
  65       percentUncacheable(_percentUncacheable),
  66       progressInterval(_progressInterval),
  67       nextProgressMessage(_progressInterval)
  68 {
  69     vector<string> cmd;
  70     cmd.push_back("/bin/ls");
  71     vector<string> null_vec;
  72     xc = new ExecContext(this ,0,mainMem,0);
  73
  74     blockSize = cacheInterface->getBlockSize();
  75     blockAddrMask = blockSize - 1;
  76     traceBlockAddr = blockAddr(_traceAddr);
  77
  78     //setup data storage with interesting values
  79     uint8_t *data1 = new uint8_t[size];
  80     uint8_t *data2 = new uint8_t[size];
  81     uint8_t *data3 = new uint8_t[size];
  82     memset(data1, 1, size);
  83     memset(data2, 2, size);
  84     memset(data3, 3, size);
  85     curTick = 0;
  86
  87     baseAddr1 = 0x100000;
  88     baseAddr2 = 0x400000;
  89     uncacheAddr = 0x800000;
  90
  91     // set up intial memory contents here
  92     mainMem->prot_write(baseAddr1, data1, size);
  93     checkMem->prot_write(baseAddr1, data1, size);
  94     mainMem->prot_write(baseAddr2, data2, size);
  95     checkMem->prot_write(baseAddr2, data2, size);
  96     mainMem->prot_write(uncacheAddr, data3, size);
  97     checkMem->prot_write(uncacheAddr, data3, size);
  98
  99     delete [] data1;
 100     delete [] data2;
 101     delete [] data3;
 102
 103     // set up counters
 104     noResponseCycles = 0;
 105     numReads = 0;
 106     numWrites = 0;
 107     tickEvent.schedule(0);
 108 }
 109
 110 static void
 111 printData(ostream &os, uint8_t *data, int nbytes)
 112 {
 113     os << hex << setfill('0');
 114     // assume little-endian: print bytes from highest address to lowest
 115     for (uint8_t *dp = data + nbytes - 1; dp >= data; --dp) {
 116         os << setw(2) << (unsigned)*dp;
 117     }
 118     os << dec;
 119 }
 120
 121 void
 122 MemTest::completeRequest(MemReqPtr req, uint8_t *data)
 123 {
 124     switch (req->cmd) {
 125       case Read:
 126         if (memcmp(req->data, data, req->size) != 0) {
 127             cerr << name() << ": on read of 0x" << hex << req->paddr
 128                  << " @ cycle " << dec << curTick
 129                  << ", cache returns 0x";
 130             printData(cerr, req->data, req->size);
 131             cerr << ", expected 0x";
 132             printData(cerr, data, req->size);
 133             cerr << endl;
 134             fatal("");
 135         }
 136
 137         numReads++;
 138
 139         if (numReads.value() == nextProgressMessage) {
 140             cerr << name() << ": completed " << numReads.value()
 141                  << " read accesses @ " << curTick << endl;
 142             nextProgressMessage += progressInterval;
 143         }
 144
 145         comLoadEventQueue[0]->serviceEvents(numReads.value());
 146         break;
 147
 148       case Write:
 149         numWrites++;
 150         break;
 151
 152
 153       default:
 154         panic("invalid command");
 155     }
 156
 157     if (blockAddr(req->paddr) == traceBlockAddr) {
 158         cerr << name() << ": completed "
 159              << (req->cmd.isWrite() ? "write" : "read") << " access of "
 160              << req->size << " bytes at address 0x"
 161              << hex << req->paddr << ", value = 0x";
 162         printData(cerr, req->data, req->size);
 163         cerr << endl;
 164     }
 165
 166     noResponseCycles = 0;
 167     delete [] data;
 168 }
 169
 170
 171 void
 172 MemTest::regStats()
 173 {
 174     using namespace Statistics;
 175
 176     numReads
 177         .name(name() + ".num_reads")
 178         .desc("number of read accesses completed")
 179         ;
 180
 181     numWrites
 182         .name(name() + ".num_writes")
 183         .desc("number of write accesses completed")
 184         ;
 185
 186     numCopies
 187         .name(name() + ".num_copies")
 188         .desc("number of copy accesses completed")
 189         ;
 190 }
 191
 192 void
 193 MemTest::tick()
 194 {
 195     if (!tickEvent.scheduled())
 196         tickEvent.schedule(curTick + 1);
 197
 198     if (++noResponseCycles >= 5000) {
 199         cerr << name() << ": deadlocked at cycle " << curTick << endl;
 200         fatal("");
 201     }
 202
 203     if (cacheInterface->isBlocked()) {
 204         return;
 205     }
 206
 207     //make new request
 208     unsigned cmd = rand() % 100;
 209     unsigned offset1 = random() % size;
 210     unsigned base = random() % 2;
 211     uint64_t data = random();
 212     unsigned access_size = random() % 4;
 213     unsigned cacheable = rand() % 100;
 214
 215     MemReqPtr req = new MemReq();
 216
 217     if (cacheable < percentUncacheable) {
 218         req->flags |= UNCACHEABLE;
 219         req->paddr = uncacheAddr + offset1;
 220     } else {
 221         req->paddr = ((base) ? baseAddr1 : baseAddr2) + offset1;
 222     }
 223
 224     req->size = 1 << access_size;
 225     req->data = new uint8_t[req->size];
 226     req->paddr &= ~(req->size - 1);
 227     req->time = curTick;
 228     req->xc = xc;
 229
 230     if (cmd < percentReads) {
 231         // read
 232         req->cmd = Read;
 233         uint8_t *result = new uint8_t[8];
 234         checkMem->access(Read, req->paddr, result, req->size);
 235         if (blockAddr(req->paddr) == traceBlockAddr) {
 236             cerr << name() << ": initiating read of "
 237                  << req->size << " bytes from addr 0x"
 238                  << hex << req->paddr << " at cycle "
 239                  << dec << curTick << endl;
 240         }
 241
 242         req->completionEvent = new MemCompleteEvent(req, result, this);
 243         cacheInterface->access(req);
 244     } else {
 245         // write
 246         req->cmd = Write;
 247         memcpy(req->data, &data, req->size);
 248         checkMem->access(Write, req->paddr, req->data, req->size);
 249         if (blockAddr(req->paddr) == traceBlockAddr) {
 250             cerr << name() << ": initiating write of "
 251                  << req->size << " bytes (value = 0x";
 252             printData(cerr, req->data, req->size);
 253             cerr << ") to addr 0x"
 254                  << hex << req->paddr << " at cycle "
 255                  << dec << curTick << endl;
 256         }
 257         req->completionEvent = new MemCompleteEvent(req, NULL, this);
 258         cacheInterface->access(req);
 259     }
 260 }
 261
 262
 263 void
 264 MemCompleteEvent::process()
 265 {
 266     tester->completeRequest(req, data);
 267     delete this;
 268 }
 269
 270
 271 const char *
 272 MemCompleteEvent::description()
 273 {
 274     return "memory access completion";
 275 }
 276
 277
 278 BEGIN_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 279
 280     SimObjectParam<BaseCache *> cache;
 281     SimObjectParam<FunctionalMemory *> main_mem;
 282     SimObjectParam<FunctionalMemory *> check_mem;
 283     Param<unsigned> memory_size;
 284     Param<unsigned> percent_reads;
 285     Param<unsigned> percent_uncacheable;
 286     Param<unsigned> progress_interval;
 287     Param<Addr> trace_addr;
 288     Param<Counter> max_loads_any_thread;
 289     Param<Counter> max_loads_all_threads;
 290
 291 END_DECLARE_SIM_OBJECT_PARAMS(MemTest)
 292
 293
 294 BEGIN_INIT_SIM_OBJECT_PARAMS(MemTest)
 295
 296     INIT_PARAM(cache, "L1 cache"),
 297     INIT_PARAM(main_mem, "hierarchical memory"),
 298     INIT_PARAM(check_mem, "check memory"),
 299     INIT_PARAM_DFLT(memory_size, "memory size", 65536),
 300     INIT_PARAM_DFLT(percent_reads, "target read percentage", 65),
 301     INIT_PARAM_DFLT(percent_uncacheable, "target uncacheable percentage", 10),
 302     INIT_PARAM_DFLT(progress_interval,
 303                     "progress report interval (in accesses)", 1000000),
 304     INIT_PARAM_DFLT(trace_addr, "address to trace", 0),
 305     INIT_PARAM_DFLT(max_loads_any_thread,
 306                     "terminate when any thread reaches this load count",
 307                     0),
 308     INIT_PARAM_DFLT(max_loads_all_threads,
 309                     "terminate when all threads have reached this load count",
 310                     0)
 311
 312 END_INIT_SIM_OBJECT_PARAMS(MemTest)
 313
 314
 315 CREATE_SIM_OBJECT(MemTest)
 316 {
 317     return new MemTest(getInstanceName(), cache->getInterface(), main_mem,
 318                        check_mem, memory_size, percent_reads,
 319                        percent_uncacheable, progress_interval,
 320                        trace_addr, max_loads_any_thread,
 321                        max_loads_all_threads);
 322 }
 323
 324 REGISTER_SIM_OBJECT("MemTest", MemTest)