cpu/o3/alpha_cpu_builder.cc

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include "base/inifile.hh"
  30 #include "base/loader/symtab.hh"
  31 #include "base/misc.hh"
  32 #include "cpu/base.hh"
  33 #include "cpu/exec_context.hh"
  34 #include "cpu/exetrace.hh"
  35 #include "cpu/o3/alpha_cpu.hh"
  36 #include "cpu/o3/alpha_impl.hh"
  37 #include "mem/base_mem.hh"
  38 #include "mem/cache/base_cache.hh"
  39 #include "mem/mem_interface.hh"
  40 #include "sim/builder.hh"
  41 #include "sim/debug.hh"
  42 #include "sim/host.hh"
  43 #include "sim/process.hh"
  44 #include "sim/sim_events.hh"
  45 #include "sim/sim_object.hh"
  46 #include "sim/stats.hh"
  47
  48 #if FULL_SYSTEM
  49 #include "base/remote_gdb.hh"
  50 #include "mem/functional/memory_control.hh"
  51 #include "mem/functional/physical.hh"
  52 #include "sim/system.hh"
  53 #include "targetarch/alpha_memory.hh"
  54 #include "targetarch/vtophys.hh"
  55 #else // !FULL_SYSTEM
  56 #include "mem/functional/functional.hh"
  57 #endif // FULL_SYSTEM
  58
  59 class DerivAlphaFullCPU : public AlphaFullCPU<AlphaSimpleImpl>
  60 {
  61   public:
  62     DerivAlphaFullCPU(AlphaSimpleParams p)
  63         : AlphaFullCPU<AlphaSimpleImpl>(p)
  64     { }
  65 };
  66
  67 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
  68
  69     Param<int> clock;
  70     Param<int> numThreads;
  71
  72 #if FULL_SYSTEM
  73 SimObjectParam<System *> system;
  74 Param<int> cpu_id;
  75 SimObjectParam<AlphaITB *> itb;
  76 SimObjectParam<AlphaDTB *> dtb;
  77 #else
  78 SimObjectVectorParam<Process *> workload;
  79 #endif // FULL_SYSTEM
  80 SimObjectParam<FunctionalMemory *> mem;
  81
  82 Param<Counter> max_insts_any_thread;
  83 Param<Counter> max_insts_all_threads;
  84 Param<Counter> max_loads_any_thread;
  85 Param<Counter> max_loads_all_threads;
  86
  87 SimObjectParam<BaseCache *> icache;
  88 SimObjectParam<BaseCache *> dcache;
  89
  90 Param<unsigned> decodeToFetchDelay;
  91 Param<unsigned> renameToFetchDelay;
  92 Param<unsigned> iewToFetchDelay;
  93 Param<unsigned> commitToFetchDelay;
  94 Param<unsigned> fetchWidth;
  95
  96 Param<unsigned> renameToDecodeDelay;
  97 Param<unsigned> iewToDecodeDelay;
  98 Param<unsigned> commitToDecodeDelay;
  99 Param<unsigned> fetchToDecodeDelay;
 100 Param<unsigned> decodeWidth;
 101
 102 Param<unsigned> iewToRenameDelay;
 103 Param<unsigned> commitToRenameDelay;
 104 Param<unsigned> decodeToRenameDelay;
 105 Param<unsigned> renameWidth;
 106
 107 Param<unsigned> commitToIEWDelay;
 108 Param<unsigned> renameToIEWDelay;
 109 Param<unsigned> issueToExecuteDelay;
 110 Param<unsigned> issueWidth;
 111 Param<unsigned> executeWidth;
 112 Param<unsigned> executeIntWidth;
 113 Param<unsigned> executeFloatWidth;
 114 Param<unsigned> executeBranchWidth;
 115 Param<unsigned> executeMemoryWidth;
 116
 117 Param<unsigned> iewToCommitDelay;
 118 Param<unsigned> renameToROBDelay;
 119 Param<unsigned> commitWidth;
 120 Param<unsigned> squashWidth;
 121
 122 #if 0
 123 Param<unsigned> localPredictorSize;
 124 Param<unsigned> localPredictorCtrBits;
 125 #endif
 126 Param<unsigned> local_predictor_size;
 127 Param<unsigned> local_ctr_bits;
 128 Param<unsigned> local_history_table_size;
 129 Param<unsigned> local_history_bits;
 130 Param<unsigned> global_predictor_size;
 131 Param<unsigned> global_ctr_bits;
 132 Param<unsigned> global_history_bits;
 133 Param<unsigned> choice_predictor_size;
 134 Param<unsigned> choice_ctr_bits;
 135
 136 Param<unsigned> BTBEntries;
 137 Param<unsigned> BTBTagSize;
 138
 139 Param<unsigned> RASSize;
 140
 141 Param<unsigned> LQEntries;
 142 Param<unsigned> SQEntries;
 143 Param<unsigned> LFSTSize;
 144 Param<unsigned> SSITSize;
 145
 146 Param<unsigned> numPhysIntRegs;
 147 Param<unsigned> numPhysFloatRegs;
 148 Param<unsigned> numIQEntries;
 149 Param<unsigned> numROBEntries;
 150
 151 Param<unsigned> instShiftAmt;
 152
 153 Param<bool> defer_registration;
 154
 155 Param<bool> function_trace;
 156 Param<Tick> function_trace_start;
 157
 158 END_DECLARE_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
 159
 160 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
 161
 162     INIT_PARAM(clock, "clock speed"),
 163     INIT_PARAM(numThreads, "number of HW thread contexts"),
 164
 165 #if FULL_SYSTEM
 166     INIT_PARAM(system, "System object"),
 167     INIT_PARAM(cpu_id, "processor ID"),
 168     INIT_PARAM(itb, "Instruction translation buffer"),
 169     INIT_PARAM(dtb, "Data translation buffer"),
 170 #else
 171     INIT_PARAM(workload, "Processes to run"),
 172 #endif // FULL_SYSTEM
 173
 174     INIT_PARAM_DFLT(mem, "Memory", NULL),
 175
 176     INIT_PARAM_DFLT(max_insts_any_thread,
 177                     "Terminate when any thread reaches this inst count",
 178                     0),
 179     INIT_PARAM_DFLT(max_insts_all_threads,
 180                     "Terminate when all threads have reached"
 181                     "this inst count",
 182                     0),
 183     INIT_PARAM_DFLT(max_loads_any_thread,
 184                     "Terminate when any thread reaches this load count",
 185                     0),
 186     INIT_PARAM_DFLT(max_loads_all_threads,
 187                     "Terminate when all threads have reached this load"
 188                     "count",
 189                     0),
 190
 191     INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 192     INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 193
 194     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 195     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 196     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 197                "delay"),
 198     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 199     INIT_PARAM(fetchWidth, "Fetch width"),
 200
 201     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 202     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 203                "delay"),
 204     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 205     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 206     INIT_PARAM(decodeWidth, "Decode width"),
 207
 208     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 209                "delay"),
 210     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 211     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 212     INIT_PARAM(renameWidth, "Rename width"),
 213
 214     INIT_PARAM(commitToIEWDelay, "Commit to "
 215                "Issue/Execute/Writeback delay"),
 216     INIT_PARAM(renameToIEWDelay, "Rename to "
 217                "Issue/Execute/Writeback delay"),
 218     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 219                "to the IEW stage)"),
 220     INIT_PARAM(issueWidth, "Issue width"),
 221     INIT_PARAM(executeWidth, "Execute width"),
 222     INIT_PARAM(executeIntWidth, "Integer execute width"),
 223     INIT_PARAM(executeFloatWidth, "Floating point execute width"),
 224     INIT_PARAM(executeBranchWidth, "Branch execute width"),
 225     INIT_PARAM(executeMemoryWidth, "Memory execute width"),
 226
 227     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 228                "delay"),
 229     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 230     INIT_PARAM(commitWidth, "Commit width"),
 231     INIT_PARAM(squashWidth, "Squash width"),
 232
 233 #if 0
 234     INIT_PARAM(localPredictorSize, "Size of the local predictor in entries. "
 235                "Must be a power of 2."),
 236     INIT_PARAM(localPredictorCtrBits, "Number of bits per counter for bpred"),
 237 #endif
 238     INIT_PARAM(local_predictor_size, "Size of local predictor"),
 239     INIT_PARAM(local_ctr_bits, "Bits per counter"),
 240     INIT_PARAM(local_history_table_size, "Size of local history table"),
 241     INIT_PARAM(local_history_bits, "Bits for the local history"),
 242     INIT_PARAM(global_predictor_size, "Size of global predictor"),
 243     INIT_PARAM(global_ctr_bits, "Bits per counter"),
 244     INIT_PARAM(global_history_bits, "Bits of history"),
 245     INIT_PARAM(choice_predictor_size, "Size of choice predictor"),
 246     INIT_PARAM(choice_ctr_bits, "Bits of choice counters"),
 247
 248     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 249     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 250
 251     INIT_PARAM(RASSize, "RAS size"),
 252
 253     INIT_PARAM(LQEntries, "Number of load queue entries"),
 254     INIT_PARAM(SQEntries, "Number of store queue entries"),
 255     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 256     INIT_PARAM(SSITSize, "Store set ID table size"),
 257
 258     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 259     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 260                "registers"),
 261     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 262     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 263
 264     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 265     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 266
 267     INIT_PARAM(function_trace, "Enable function trace"),
 268     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 269
 270 END_INIT_SIM_OBJECT_PARAMS(DerivAlphaFullCPU)
 271
 272 CREATE_SIM_OBJECT(DerivAlphaFullCPU)
 273 {
 274     DerivAlphaFullCPU *cpu;
 275
 276 #if FULL_SYSTEM
 277     // Full-system only supports a single thread for the moment.
 278     int actual_num_threads = 1;
 279 #else
 280     // In non-full-system mode, we infer the number of threads from
 281     // the workload if it's not explicitly specified.
 282     int actual_num_threads =
 283         numThreads.isValid() ? numThreads : workload.size();
 284
 285     if (workload.size() == 0) {
 286         fatal("Must specify at least one workload!");
 287     }
 288
 289 #endif
 290
 291     AlphaSimpleParams params;
 292
 293     params.clock = clock;
 294
 295     params.name = getInstanceName();
 296     params.numberOfThreads = actual_num_threads;
 297
 298 #if FULL_SYSTEM
 299     params.system = system;
 300     params.cpu_id = cpu_id;
 301     params.itb = itb;
 302     params.dtb = dtb;
 303 #else
 304     params.workload = workload;
 305 #endif // FULL_SYSTEM
 306
 307     params.mem = mem;
 308
 309     params.max_insts_any_thread = max_insts_any_thread;
 310     params.max_insts_all_threads = max_insts_all_threads;
 311     params.max_loads_any_thread = max_loads_any_thread;
 312     params.max_loads_all_threads = max_loads_all_threads;
 313
 314     //
 315     // Caches
 316     //
 317     params.icacheInterface = icache ? icache->getInterface() : NULL;
 318     params.dcacheInterface = dcache ? dcache->getInterface() : NULL;
 319
 320     params.decodeToFetchDelay = decodeToFetchDelay;
 321     params.renameToFetchDelay = renameToFetchDelay;
 322     params.iewToFetchDelay = iewToFetchDelay;
 323     params.commitToFetchDelay = commitToFetchDelay;
 324     params.fetchWidth = fetchWidth;
 325
 326     params.renameToDecodeDelay = renameToDecodeDelay;
 327     params.iewToDecodeDelay = iewToDecodeDelay;
 328     params.commitToDecodeDelay = commitToDecodeDelay;
 329     params.fetchToDecodeDelay = fetchToDecodeDelay;
 330     params.decodeWidth = decodeWidth;
 331
 332     params.iewToRenameDelay = iewToRenameDelay;
 333     params.commitToRenameDelay = commitToRenameDelay;
 334     params.decodeToRenameDelay = decodeToRenameDelay;
 335     params.renameWidth = renameWidth;
 336
 337     params.commitToIEWDelay = commitToIEWDelay;
 338     params.renameToIEWDelay = renameToIEWDelay;
 339     params.issueToExecuteDelay = issueToExecuteDelay;
 340     params.issueWidth = issueWidth;
 341     params.executeWidth = executeWidth;
 342     params.executeIntWidth = executeIntWidth;
 343     params.executeFloatWidth = executeFloatWidth;
 344     params.executeBranchWidth = executeBranchWidth;
 345     params.executeMemoryWidth = executeMemoryWidth;
 346
 347     params.iewToCommitDelay = iewToCommitDelay;
 348     params.renameToROBDelay = renameToROBDelay;
 349     params.commitWidth = commitWidth;
 350     params.squashWidth = squashWidth;
 351 #if 0
 352     params.localPredictorSize = localPredictorSize;
 353     params.localPredictorCtrBits = localPredictorCtrBits;
 354 #endif
 355     params.local_predictor_size = local_predictor_size;
 356     params.local_ctr_bits = local_ctr_bits;
 357     params.local_history_table_size = local_history_table_size;
 358     params.local_history_bits = local_history_bits;
 359     params.global_predictor_size = global_predictor_size;
 360     params.global_ctr_bits = global_ctr_bits;
 361     params.global_history_bits = global_history_bits;
 362     params.choice_predictor_size = choice_predictor_size;
 363     params.choice_ctr_bits = choice_ctr_bits;
 364
 365     params.BTBEntries = BTBEntries;
 366     params.BTBTagSize = BTBTagSize;
 367
 368     params.RASSize = RASSize;
 369
 370     params.LQEntries = LQEntries;
 371     params.SQEntries = SQEntries;
 372     params.SSITSize = SSITSize;
 373     params.LFSTSize = LFSTSize;
 374
 375     params.numPhysIntRegs = numPhysIntRegs;
 376     params.numPhysFloatRegs = numPhysFloatRegs;
 377     params.numIQEntries = numIQEntries;
 378     params.numROBEntries = numROBEntries;
 379
 380     params.instShiftAmt = 2;
 381
 382     params.defReg = defer_registration;
 383
 384     params.functionTrace = function_trace;
 385     params.functionTraceStart = function_trace_start;
 386
 387     cpu = new DerivAlphaFullCPU(params);
 388
 389     return cpu;
 390 }
 391
 392 REGISTER_SIM_OBJECT("DerivAlphaFullCPU", DerivAlphaFullCPU)
 393