Merge zizzer.eecs.umich.edu:/z/m5/Bitkeeper/m5
[gem5.git] / cpu / o3 / btb.hh
1 /*
2 * Copyright (c) 2004-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 #ifndef __CPU_O3_CPU_BTB_HH__
30 #define __CPU_O3_CPU_BTB_HH__
31
32 // For Addr type.
33 #include "arch/isa_traits.hh"
34
35 class DefaultBTB
36 {
37 private:
38 struct BTBEntry
39 {
40 BTBEntry()
41 : tag(0), target(0), valid(false)
42 {
43 }
44
45 Addr tag;
46 Addr target;
47 bool valid;
48 };
49
50 public:
51 DefaultBTB(unsigned numEntries, unsigned tagBits,
52 unsigned instShiftAmt);
53
54 Addr lookup(const Addr &inst_PC);
55
56 bool valid(const Addr &inst_PC);
57
58 void update(const Addr &inst_PC, const Addr &target_PC);
59
60 private:
61 inline unsigned getIndex(const Addr &inst_PC);
62
63 inline Addr getTag(const Addr &inst_PC);
64
65 BTBEntry *btb;
66
67 unsigned numEntries;
68
69 unsigned idxMask;
70
71 unsigned tagBits;
72
73 unsigned tagMask;
74
75 unsigned instShiftAmt;
76
77 unsigned tagShiftAmt;
78 };
79
80 #endif // __CPU_O3_CPU_BTB_HH__