cpu/o3/commit.hh

   1 /*
   2  * Copyright (c) 2004-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_O3_COMMIT_HH__
  30 #define __CPU_O3_COMMIT_HH__
  31
  32 #include "arch/faults.hh"
  33 #include "cpu/inst_seq.hh"
  34 #include "base/statistics.hh"
  35 #include "base/timebuf.hh"
  36 #include "cpu/exetrace.hh"
  37 #include "mem/memory_interface.hh"
  38
  39 template <class>
  40 class O3ThreadState;
  41
  42 /**
  43  * DefaultCommit handles single threaded and SMT commit. Its width is specified
  44  * by the parameters; each cycle it tries to commit that many instructions. The
  45  * SMT policy decides which thread it tries to commit instructions from. Non-
  46  * speculative instructions must reach the head of the ROB before they are
  47  * ready to execute; once they reach the head, commit will broadcast the
  48  * instruction's sequence number to the previous stages so that they can issue/
  49  * execute the instruction. Only one non-speculative instruction is handled per
  50  * cycle. Commit is responsible for handling all back-end initiated redirects.
  51  * It receives the redirect, and then broadcasts it to all stages, indicating
  52  * the sequence number they should squash until, and any necessary branch mis-
  53  * prediction information as well. It priortizes redirects by instruction's age,
  54  * only broadcasting a redirect if it corresponds to an instruction that should
  55  * currently be in the ROB. This is done by tracking the sequence number of the
  56  * youngest instruction in the ROB, which gets updated to any squashing
  57  * instruction's sequence number, and only broadcasting a redirect if it
  58  * corresponds to an older instruction. Commit also supports multiple cycle
  59  * squashing, to model a ROB that can only remove a certain number of
  60  * instructions per cycle. Eventually traps and interrupts will most likely
  61  * be handled here as well.
  62  */
  63 template<class Impl>
  64 class DefaultCommit
  65 {
  66   public:
  67     // Typedefs from the Impl.
  68     typedef typename Impl::FullCPU FullCPU;
  69     typedef typename Impl::DynInstPtr DynInstPtr;
  70     typedef typename Impl::Params Params;
  71     typedef typename Impl::CPUPol CPUPol;
  72
  73     typedef typename CPUPol::RenameMap RenameMap;
  74     typedef typename CPUPol::ROB ROB;
  75
  76     typedef typename CPUPol::TimeStruct TimeStruct;
  77     typedef typename CPUPol::FetchStruct FetchStruct;
  78     typedef typename CPUPol::IEWStruct IEWStruct;
  79     typedef typename CPUPol::RenameStruct RenameStruct;
  80
  81     typedef typename CPUPol::IEW IEW;
  82
  83     typedef O3ThreadState<Impl> Thread;
  84
  85     class TrapEvent : public Event {
  86       private:
  87         DefaultCommit<Impl> *commit;
  88         unsigned tid;
  89
  90       public:
  91         TrapEvent(DefaultCommit<Impl> *_commit, unsigned _tid);
  92
  93         void process();
  94         const char *description();
  95     };
  96
  97     /** Overall commit status. Used to determine if the CPU can deschedule
  98      * itself due to a lack of activity.
  99      */
 100     enum CommitStatus{
 101         Active,
 102         Inactive
 103     };
 104
 105     /** Individual thread status. */
 106     enum ThreadStatus {
 107         Running,
 108         Idle,
 109         ROBSquashing,
 110         TrapPending,
 111         FetchTrapPending
 112     };
 113
 114     /** Commit policy for SMT mode. */
 115     enum CommitPolicy {
 116         Aggressive,
 117         RoundRobin,
 118         OldestReady
 119     };
 120
 121   private:
 122     /** Overall commit status. */
 123     CommitStatus _status;
 124     /** Next commit status, to be set at the end of the cycle. */
 125     CommitStatus _nextStatus;
 126     /** Per-thread status. */
 127     ThreadStatus commitStatus[Impl::MaxThreads];
 128     /** Commit policy used in SMT mode. */
 129     CommitPolicy commitPolicy;
 130
 131   public:
 132     /** Construct a DefaultCommit with the given parameters. */
 133     DefaultCommit(Params *params);
 134
 135     /** Returns the name of the DefaultCommit. */
 136     std::string name() const;
 137
 138     /** Registers statistics. */
 139     void regStats();
 140
 141     /** Sets the CPU pointer. */
 142     void setCPU(FullCPU *cpu_ptr);
 143
 144     /** Sets the list of threads. */
 145     void setThreads(std::vector<Thread *> &threads);
 146
 147     /** Sets the main time buffer pointer, used for backwards communication. */
 148     void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
 149
 150     void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
 151
 152     /** Sets the pointer to the queue coming from rename. */
 153     void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
 154
 155     /** Sets the pointer to the queue coming from IEW. */
 156     void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
 157
 158     /** Sets the poitner to the IEW stage. */
 159     void setIEWStage(IEW *iew_stage);
 160
 161     /** The pointer to the IEW stage. Used solely to ensure that syscalls do
 162      * not execute until all stores have written back.
 163      */
 164     IEW *iewStage;
 165
 166     /** Sets pointer to list of active threads. */
 167     void setActiveThreads(std::list<unsigned> *at_ptr);
 168
 169     /** Sets pointer to the commited state rename map. */
 170     void setRenameMap(RenameMap rm_ptr[Impl::MaxThreads]);
 171
 172     /** Sets pointer to the ROB. */
 173     void setROB(ROB *rob_ptr);
 174
 175     /** Initializes stage by sending back the number of free entries. */
 176     void initStage();
 177
 178     void switchOut();
 179
 180     void takeOverFrom();
 181
 182     /** Ticks the commit stage, which tries to commit instructions. */
 183     void tick();
 184
 185     /** Handles any squashes that are sent from IEW, and adds instructions
 186      * to the ROB and tries to commit instructions.
 187      */
 188     void commit();
 189
 190     /** Returns the number of free ROB entries for a specific thread. */
 191     unsigned numROBFreeEntries(unsigned tid);
 192
 193     void generateXCEvent(unsigned tid);
 194
 195   private:
 196     /** Updates the overall status of commit with the nextStatus, and
 197      * tell the CPU if commit is active/inactive. */
 198     void updateStatus();
 199
 200     /** Sets the next status based on threads' statuses, which becomes the
 201      * current status at the end of the cycle.
 202      */
 203     void setNextStatus();
 204
 205     /** Checks if the ROB is completed with squashing. This is for the case
 206      * where the ROB can take multiple cycles to complete squashing.
 207      */
 208     bool robDoneSquashing();
 209
 210     /** Returns if any of the threads have the number of ROB entries changed
 211      * on this cycle. Used to determine if the number of free ROB entries needs
 212      * to be sent back to previous stages.
 213      */
 214     bool changedROBEntries();
 215
 216     void squashFromTrap(unsigned tid);
 217
 218     void squashFromXC(unsigned tid);
 219
 220     void squashInFlightInsts(unsigned tid);
 221
 222   private:
 223     /** Commits as many instructions as possible. */
 224     void commitInsts();
 225
 226     /** Tries to commit the head ROB instruction passed in.
 227      * @param head_inst The instruction to be committed.
 228      */
 229     bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
 230
 231     void generateTrapEvent(unsigned tid);
 232
 233     /** Gets instructions from rename and inserts them into the ROB. */
 234     void getInsts();
 235
 236     /** Marks completed instructions using information sent from IEW. */
 237     void markCompletedInsts();
 238
 239     /** Gets the thread to commit, based on the SMT policy. */
 240     int getCommittingThread();
 241
 242     /** Returns the thread ID to use based on a round robin policy. */
 243     int roundRobin();
 244
 245     /** Returns the thread ID to use based on an oldest instruction policy. */
 246     int oldestReady();
 247
 248   public:
 249     /** Returns the PC of the head instruction of the ROB. */
 250     uint64_t readPC();
 251
 252     uint64_t readPC(unsigned tid) { return PC[tid]; }
 253
 254     void setPC(uint64_t val, unsigned tid) { PC[tid] = val; }
 255
 256     uint64_t readNextPC(unsigned tid) { return nextPC[tid]; }
 257
 258     void setNextPC(uint64_t val, unsigned tid) { nextPC[tid] = val; }
 259
 260     /** Sets that the ROB is currently squashing. */
 261     void setSquashing(unsigned tid);
 262
 263   private:
 264     /** Time buffer interface. */
 265     TimeBuffer<TimeStruct> *timeBuffer;
 266
 267     /** Wire to write information heading to previous stages. */
 268     typename TimeBuffer<TimeStruct>::wire toIEW;
 269
 270     /** Wire to read information from IEW (for ROB). */
 271     typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
 272
 273     TimeBuffer<FetchStruct> *fetchQueue;
 274
 275     typename TimeBuffer<FetchStruct>::wire fromFetch;
 276
 277     /** IEW instruction queue interface. */
 278     TimeBuffer<IEWStruct> *iewQueue;
 279
 280     /** Wire to read information from IEW queue. */
 281     typename TimeBuffer<IEWStruct>::wire fromIEW;
 282
 283     /** Rename instruction queue interface, for ROB. */
 284     TimeBuffer<RenameStruct> *renameQueue;
 285
 286     /** Wire to read information from rename queue. */
 287     typename TimeBuffer<RenameStruct>::wire fromRename;
 288
 289   public:
 290     /** ROB interface. */
 291     ROB *rob;
 292
 293   private:
 294     /** Pointer to FullCPU. */
 295     FullCPU *cpu;
 296
 297     /** Memory interface.  Used for d-cache accesses. */
 298     MemInterface *dcacheInterface;
 299
 300     std::vector<Thread *> thread;
 301
 302   private:
 303     Fault fetchFault;
 304     InstSeqNum fetchFaultSN;
 305     int fetchTrapWait;
 306     /** Records that commit has written to the time buffer this cycle. Used for
 307      * the CPU to determine if it can deschedule itself if there is no activity.
 308      */
 309     bool wroteToTimeBuffer;
 310
 311     /** Records if the number of ROB entries has changed this cycle. If it has,
 312      * then the number of free entries must be re-broadcast.
 313      */
 314     bool changedROBNumEntries[Impl::MaxThreads];
 315
 316     /** A counter of how many threads are currently squashing. */
 317     int squashCounter;
 318
 319     /** Records if a thread has to squash this cycle due to a trap. */
 320     bool trapSquash[Impl::MaxThreads];
 321
 322     /** Records if a thread has to squash this cycle due to an XC write. */
 323     bool xcSquash[Impl::MaxThreads];
 324
 325     /** Priority List used for Commit Policy */
 326     std::list<unsigned> priority_list;
 327
 328     /** IEW to Commit delay, in ticks. */
 329     unsigned iewToCommitDelay;
 330
 331     /** Commit to IEW delay, in ticks. */
 332     unsigned commitToIEWDelay;
 333
 334     /** Rename to ROB delay, in ticks. */
 335     unsigned renameToROBDelay;
 336
 337     unsigned fetchToCommitDelay;
 338
 339     /** Rename width, in instructions.  Used so ROB knows how many
 340      *  instructions to get from the rename instruction queue.
 341      */
 342     unsigned renameWidth;
 343
 344     /** IEW width, in instructions.  Used so ROB knows how many
 345      *  instructions to get from the IEW instruction queue.
 346      */
 347     unsigned iewWidth;
 348
 349     /** Commit width, in instructions. */
 350     unsigned commitWidth;
 351
 352     /** Number of Reorder Buffers */
 353     unsigned numRobs;
 354
 355     /** Number of Active Threads */
 356     unsigned numThreads;
 357
 358     bool switchedOut;
 359
 360     Tick trapLatency;
 361
 362     Tick fetchTrapLatency;
 363     Tick fetchFaultTick;
 364
 365     Addr PC[Impl::MaxThreads];
 366
 367     Addr nextPC[Impl::MaxThreads];
 368
 369     /** The sequence number of the youngest valid instruction in the ROB. */
 370     InstSeqNum youngestSeqNum[Impl::MaxThreads];
 371
 372     /** Pointer to the list of active threads. */
 373     std::list<unsigned> *activeThreads;
 374
 375     /** Rename map interface. */
 376     RenameMap *renameMap[Impl::MaxThreads];
 377
 378     void updateComInstStats(DynInstPtr &inst);
 379
 380     /** Stat for the total number of committed instructions. */
 381     Stats::Scalar<> commitCommittedInsts;
 382     /** Stat for the total number of squashed instructions discarded by commit.
 383      */
 384     Stats::Scalar<> commitSquashedInsts;
 385     /** Stat for the total number of times commit is told to squash.
 386      * @todo: Actually increment this stat.
 387      */
 388     Stats::Scalar<> commitSquashEvents;
 389     /** Stat for the total number of times commit has had to stall due to a non-
 390      * speculative instruction reaching the head of the ROB.
 391      */
 392     Stats::Scalar<> commitNonSpecStalls;
 393     /** Stat for the total number of committed branches. */
 394 //    Stats::Scalar<> commitCommittedBranches;
 395     /** Stat for the total number of committed loads. */
 396 //    Stats::Scalar<> commitCommittedLoads;
 397     /** Stat for the total number of committed memory references. */
 398 //    Stats::Scalar<> commitCommittedMemRefs;
 399     /** Stat for the total number of branch mispredicts that caused a squash. */
 400     Stats::Scalar<> branchMispredicts;
 401     /** Distribution of the number of committed instructions each cycle. */
 402     Stats::Distribution<> numCommittedDist;
 403
 404     // total number of instructions committed
 405     Stats::Vector<> stat_com_inst;
 406     Stats::Vector<> stat_com_swp;
 407     Stats::Vector<> stat_com_refs;
 408     Stats::Vector<> stat_com_loads;
 409     Stats::Vector<> stat_com_membars;
 410     Stats::Vector<> stat_com_branches;
 411
 412     Stats::Scalar<> commit_eligible_samples;
 413     Stats::Vector<> commit_eligible;
 414 };
 415
 416 #endif // __CPU_O3_COMMIT_HH__