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29 // Todo: Maybe have a special method for handling interrupts/traps.
31 // Traps: Have IEW send a signal to commit saying that there's a trap to
32 // be handled. Have commit send the PC back to the fetch stage, along
33 // with the current commit PC. Fetch will directly access the IPR and save
34 // off all the proper stuff. Commit can send out a squash, or something
36 // Do the same for hwrei(). However, requires that commit be specifically
37 // built to support that kind of stuff. Probably not horrible to have
38 // commit support having the CPU tell it to squash the other stages and
39 // restart at a given address. The IPR register does become an issue.
40 // Probably not a big deal if the IPR stuff isn't cycle accurate. Can just
41 // have the original function handle writing to the IPR register.
43 #ifndef __CPU_O3_CPU_SIMPLE_COMMIT_HH__
44 #define __CPU_O3_CPU_SIMPLE_COMMIT_HH__
46 #include "base/statistics.hh"
47 #include "base/timebuf.hh"
48 #include "mem/memory_interface.hh"
54 // Typedefs from the Impl.
55 typedef typename Impl::ISA ISA;
56 typedef typename Impl::FullCPU FullCPU;
57 typedef typename Impl::DynInstPtr DynInstPtr;
58 typedef typename Impl::Params Params;
59 typedef typename Impl::CPUPol CPUPol;
61 typedef typename CPUPol::ROB ROB;
63 typedef typename CPUPol::TimeStruct TimeStruct;
64 typedef typename CPUPol::IEWStruct IEWStruct;
65 typedef typename CPUPol::RenameStruct RenameStruct;
68 // I don't believe commit can block, so it will only have two
70 // Actually if there's a cache access that needs to block (ie
71 // uncachable load or just a mem access in commit) then the stage
85 SimpleCommit(Params ¶ms);
89 void setCPU(FullCPU *cpu_ptr);
91 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
93 void setRenameQueue(TimeBuffer<RenameStruct> *rq_ptr);
95 void setIEWQueue(TimeBuffer<IEWStruct> *iq_ptr);
97 void setROB(ROB *rob_ptr);
107 bool commitHead(DynInstPtr &head_inst, unsigned inst_num);
111 void markCompletedInsts();
114 uint64_t readCommitPC();
116 void setSquashing() { _status = ROBSquashing; }
119 /** Time buffer interface. */
120 TimeBuffer<TimeStruct> *timeBuffer;
122 /** Wire to write information heading to previous stages. */
123 typename TimeBuffer<TimeStruct>::wire toIEW;
125 /** Wire to read information from IEW (for ROB). */
126 typename TimeBuffer<TimeStruct>::wire robInfoFromIEW;
128 /** IEW instruction queue interface. */
129 TimeBuffer<IEWStruct> *iewQueue;
131 /** Wire to read information from IEW queue. */
132 typename TimeBuffer<IEWStruct>::wire fromIEW;
134 /** Rename instruction queue interface, for ROB. */
135 TimeBuffer<RenameStruct> *renameQueue;
137 /** Wire to read information from rename queue. */
138 typename TimeBuffer<RenameStruct>::wire fromRename;
140 /** ROB interface. */
143 /** Pointer to FullCPU. */
146 /** Memory interface. Used for d-cache accesses. */
147 MemInterface *dcacheInterface;
150 /** IEW to Commit delay, in ticks. */
151 unsigned iewToCommitDelay;
153 /** Rename to ROB delay, in ticks. */
154 unsigned renameToROBDelay;
156 /** Rename width, in instructions. Used so ROB knows how many
157 * instructions to get from the rename instruction queue.
159 unsigned renameWidth;
161 /** IEW width, in instructions. Used so ROB knows how many
162 * instructions to get from the IEW instruction queue.
166 /** Commit width, in instructions. */
167 unsigned commitWidth;
169 Stats::Scalar<> commitCommittedInsts;
170 Stats::Scalar<> commitSquashedInsts;
171 Stats::Scalar<> commitSquashEvents;
172 Stats::Scalar<> commitNonSpecStalls;
173 Stats::Scalar<> commitCommittedBranches;
174 Stats::Scalar<> commitCommittedLoads;
175 Stats::Scalar<> commitCommittedMemRefs;
176 Stats::Scalar<> branchMispredicts;
178 Stats::Distribution<> n_committed_dist;
181 #endif // __CPU_O3_CPU_SIMPLE_COMMIT_HH__