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29 #ifndef __CPU_O3_CPU_SIMPLE_DECODE_HH__
30 #define __CPU_O3_CPU_SIMPLE_DECODE_HH__
34 #include "base/statistics.hh"
35 #include "base/timebuf.hh"
41 // Typedefs from the Impl.
42 typedef typename Impl::FullCPU FullCPU;
43 typedef typename Impl::DynInstPtr DynInstPtr;
44 typedef typename Impl::Params Params;
45 typedef typename Impl::CPUPol CPUPol;
47 // Typedefs from the CPU policy.
48 typedef typename CPUPol::FetchStruct FetchStruct;
49 typedef typename CPUPol::DecodeStruct DecodeStruct;
50 typedef typename CPUPol::TimeStruct TimeStruct;
53 // The only time decode will become blocked is if dispatch becomes
54 // blocked, which means IQ or ROB is probably full.
64 // May eventually need statuses on a per thread basis.
68 SimpleDecode(Params ¶ms);
72 void setCPU(FullCPU *cpu_ptr);
74 void setTimeBuffer(TimeBuffer<TimeStruct> *tb_ptr);
76 void setDecodeQueue(TimeBuffer<DecodeStruct> *dq_ptr);
78 void setFetchQueue(TimeBuffer<FetchStruct> *fq_ptr);
85 inline bool fetchInstsValid();
89 inline void unblock();
91 void squash(DynInstPtr &inst);
94 // Might want to make squash a friend function.
98 // Interfaces to objects outside of decode.
102 /** Time buffer interface. */
103 TimeBuffer<TimeStruct> *timeBuffer;
105 /** Wire to get rename's output from backwards time buffer. */
106 typename TimeBuffer<TimeStruct>::wire fromRename;
108 /** Wire to get iew's information from backwards time buffer. */
109 typename TimeBuffer<TimeStruct>::wire fromIEW;
111 /** Wire to get commit's information from backwards time buffer. */
112 typename TimeBuffer<TimeStruct>::wire fromCommit;
114 /** Wire to write information heading to previous stages. */
115 // Might not be the best name as not only fetch will read it.
116 typename TimeBuffer<TimeStruct>::wire toFetch;
118 /** Decode instruction queue. */
119 TimeBuffer<DecodeStruct> *decodeQueue;
121 /** Wire used to write any information heading to rename. */
122 typename TimeBuffer<DecodeStruct>::wire toRename;
124 /** Fetch instruction queue interface. */
125 TimeBuffer<FetchStruct> *fetchQueue;
127 /** Wire to get fetch's output from fetch queue. */
128 typename TimeBuffer<FetchStruct>::wire fromFetch;
130 /** Skid buffer between fetch and decode. */
131 std::queue<FetchStruct> skidBuffer;
133 //Consider making these unsigned to avoid any confusion.
134 /** Rename to decode delay, in ticks. */
135 unsigned renameToDecodeDelay;
137 /** IEW to decode delay, in ticks. */
138 unsigned iewToDecodeDelay;
140 /** Commit to decode delay, in ticks. */
141 unsigned commitToDecodeDelay;
143 /** Fetch to decode delay, in ticks. */
144 unsigned fetchToDecodeDelay;
146 /** The width of decode, in instructions. */
147 unsigned decodeWidth;
149 /** The instruction that decode is currently on. It needs to have
150 * persistent state so that when a stall occurs in the middle of a
151 * group of instructions, it can restart at the proper instruction.
155 Stats::Scalar<> decodeIdleCycles;
156 Stats::Scalar<> decodeBlockedCycles;
157 Stats::Scalar<> decodeUnblockCycles;
158 Stats::Scalar<> decodeSquashCycles;
159 Stats::Scalar<> decodeBranchMispred;
160 Stats::Scalar<> decodeControlMispred;
161 Stats::Scalar<> decodeDecodedInsts;
162 Stats::Scalar<> decodeSquashedInsts;
165 #endif // __CPU_O3_CPU_SIMPLE_DECODE_HH__