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29 #ifndef __CPU_OOO_CPU_OOO_CPU_HH__
30 #define __CPU_OOO_CPU_OOO_CPU_HH__
32 #include "base/statistics.hh"
33 #include "cpu/base_cpu.hh"
34 #include "cpu/exec_context.hh"
35 #include "cpu/full_cpu/fu_pool.hh"
36 #include "cpu/ooo_cpu/ea_list.hh"
37 #include "cpu/pc_event.hh"
38 #include "cpu/static_inst.hh"
39 #include "mem/mem_interface.hh"
40 #include "sim/eventq.hh"
42 // forward declarations
66 * Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
67 * simple out-of-order capabilities added to it. It is still a 1 CPI machine
68 * (?), but is capable of handling cache misses. Basically it models having
69 * a ROB/IQ by only allowing a certain amount of instructions to execute while
70 * the cache miss is outstanding.
74 class OoOCPU : public BaseCPU
77 typedef typename Impl::DynInst DynInst;
78 typedef typename Impl::DynInstPtr DynInstPtr;
79 typedef typename Impl::ISA ISA;
82 // main simulation loop (one cycle)
86 struct TickEvent : public Event
91 TickEvent(OoOCPU *c, int w);
93 const char *description();
98 /// Schedule tick event, regardless of its current state.
99 void scheduleTickEvent(int delay)
101 if (tickEvent.squashed())
102 tickEvent.reschedule(curTick + delay);
103 else if (!tickEvent.scheduled())
104 tickEvent.schedule(curTick + delay);
107 /// Unschedule tick event, regardless of its current state.
108 void unscheduleTickEvent()
110 if (tickEvent.scheduled())
115 Trace::InstRecord *traceData;
118 void trace_data(T data);
135 void post_interrupt(int int_num, int index);
137 void zero_fill_64(Addr addr) {
138 static int warned = 0;
140 warn ("WH64 is not implemented");
145 struct Params : public BaseCPU::Params
147 MemInterface *icache_interface;
148 MemInterface *dcache_interface;
153 FunctionalMemory *mem;
160 OoOCPU(Params *params);
172 void takeOverFrom(BaseCPU *oldCPU);
175 Addr dbg_vtophys(Addr addr);
180 // L1 instruction cache
181 MemInterface *icacheInterface;
184 MemInterface *dcacheInterface;
186 FuncUnitPool *fuPool;
188 // Refcounted pointer to the one memory request.
189 MemReqPtr cacheMemReq;
191 class ICacheCompletionEvent : public Event
197 ICacheCompletionEvent(OoOCPU *_cpu);
199 virtual void process();
200 virtual const char *description();
203 // Will need to create a cache completion event upon any memory miss.
204 ICacheCompletionEvent iCacheCompletionEvent;
206 class DCacheCompletionEvent : public Event
213 DCacheCompletionEvent(OoOCPU *_cpu, DynInstPtr &_inst);
215 virtual void process();
216 virtual const char *description();
219 friend class DCacheCompletionEvent;
221 Status status() const { return _status; }
223 virtual void activateContext(int thread_num, int delay);
224 virtual void suspendContext(int thread_num);
225 virtual void deallocateContext(int thread_num);
226 virtual void haltContext(int thread_num);
229 virtual void regStats();
230 virtual void resetStats();
232 // number of simulated instructions
234 Counter startNumInst;
235 Stats::Scalar<> numInsts;
237 virtual Counter totalInstructions() const
239 return numInst - startNumInst;
242 // number of simulated memory references
243 Stats::Scalar<> numMemRefs;
245 // number of simulated loads
247 Counter startNumLoad;
249 // number of idle cycles
250 Stats::Average<> notIdleFraction;
251 Stats::Formula idleFraction;
253 // number of cycles stalled for I-cache misses
254 Stats::Scalar<> icacheStallCycles;
255 Counter lastIcacheStall;
257 // number of cycles stalled for D-cache misses
258 Stats::Scalar<> dcacheStallCycles;
259 Counter lastDcacheStall;
261 void processICacheCompletion();
263 virtual void serialize(std::ostream &os);
264 virtual void unserialize(Checkpoint *cp, const std::string §ion);
267 bool validInstAddr(Addr addr) { return true; }
268 bool validDataAddr(Addr addr) { return true; }
269 int getInstAsid() { return xc->regs.instAsid(); }
270 int getDataAsid() { return xc->regs.dataAsid(); }
272 Fault translateInstReq(MemReqPtr &req)
274 return itb->translate(req);
277 Fault translateDataReadReq(MemReqPtr &req)
279 return dtb->translate(req, false);
282 Fault translateDataWriteReq(MemReqPtr &req)
284 return dtb->translate(req, true);
288 bool validInstAddr(Addr addr)
289 { return xc->validInstAddr(addr); }
291 bool validDataAddr(Addr addr)
292 { return xc->validDataAddr(addr); }
294 int getInstAsid() { return xc->asid; }
295 int getDataAsid() { return xc->asid; }
297 Fault dummyTranslation(MemReqPtr &req)
300 assert((req->vaddr >> 48 & 0xffff) == 0);
303 // put the asid in the upper 16 bits of the paddr
304 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
305 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
308 Fault translateInstReq(MemReqPtr &req)
310 return dummyTranslation(req);
312 Fault translateDataReadReq(MemReqPtr &req)
314 return dummyTranslation(req);
316 Fault translateDataWriteReq(MemReqPtr &req)
318 return dummyTranslation(req);
324 Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
327 Fault write(T data, Addr addr, unsigned flags,
328 uint64_t *res, DynInstPtr inst);
330 void prefetch(Addr addr, unsigned flags)
332 // need to do this...
335 void writeHint(Addr addr, int size, unsigned flags)
337 // need to do this...
340 Fault copySrcTranslate(Addr src);
342 Fault copy(Addr dest);
345 bool executeInst(DynInstPtr &inst);
347 void renameInst(DynInstPtr &inst);
349 void addInst(DynInstPtr &inst);
351 void commitHeadInst();
355 Fault fetchCacheLine();
357 InstSeqNum getAndIncrementInstSeq();
362 InstSeqNum globalSeqNum;
364 DynInstPtr renameTable[ISA::TotalNumRegs];
365 DynInstPtr commitTable[ISA::TotalNumRegs];
367 // Might need a table of the shadow registers as well.
369 DynInstPtr palShadowTable[ISA::NumIntRegs];
373 // The register accessor methods provide the index of the
374 // instruction's operand (e.g., 0 or 1), not the architectural
375 // register index, to simplify the implementation of register
376 // renaming. We find the architectural register index by indexing
377 // into the instruction's own operand index table. Note that a
378 // raw pointer to the StaticInst is provided instead of a
379 // ref-counted StaticInstPtr to redice overhead. This is fine as
380 // long as these methods don't copy the pointer into any long-term
381 // storage (which is pretty hard to imagine they would have reason
384 // In the OoO case these shouldn't read from the XC but rather from the
385 // rename table of DynInsts. Also these likely shouldn't be called very
386 // often, other than when adding things into the xc during say a syscall.
388 uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
390 return xc->readIntReg(si->srcRegIdx(idx));
393 float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
395 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
396 return xc->readFloatRegSingle(reg_idx);
399 double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
401 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
402 return xc->readFloatRegDouble(reg_idx);
405 uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
407 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
408 return xc->readFloatRegInt(reg_idx);
411 void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
413 xc->setIntReg(si->destRegIdx(idx), val);
416 void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
418 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
419 xc->setFloatRegSingle(reg_idx, val);
422 void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
424 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
425 xc->setFloatRegDouble(reg_idx, val);
428 void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
430 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
431 xc->setFloatRegInt(reg_idx, val);
434 uint64_t readPC() { return PC; }
435 void setNextPC(Addr val) { nextPC = val; }
444 bool fetchRedirBranch;
446 /** Mask to get a cache block's address. */
449 unsigned cacheBlkSize;
453 /** The cache line being fetched. */
461 // Align an address (typically a PC) to the start of an I-cache block.
462 // We fold in the PISA 64- to 32-bit conversion here as well.
463 Addr icacheBlockAlignPC(Addr addr)
465 addr = ISA::realPCToFetchPC(addr);
466 return (addr & ~(cacheBlkMask));
471 // ROB tracking stuff.
472 DynInstPtr robHeadPtr;
473 DynInstPtr robTailPtr;
476 // List of outstanding EA instructions.
481 void branchToTarget(Addr val)
483 if (!fetchRedirExcp) {
484 fetchRedirBranch = true;
490 uint64_t readUniq() { return xc->readUniq(); }
491 void setUniq(uint64_t val) { xc->setUniq(val); }
493 uint64_t readFpcr() { return xc->readFpcr(); }
494 void setFpcr(uint64_t val) { xc->setFpcr(val); }
497 uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
498 Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
499 Fault hwrei() { return xc->hwrei(); }
500 int readIntrFlag() { return xc->readIntrFlag(); }
501 void setIntrFlag(int val) { xc->setIntrFlag(val); }
502 bool inPalMode() { return xc->inPalMode(); }
503 void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
504 bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
506 void syscall() { xc->syscall(); }
509 ExecContext *xcBase() { return xc; }
513 // precise architected memory state accessor macros
514 template <class Impl>
517 OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
519 MemReqPtr readReq = new MemReq();
522 readReq->data = new uint8_t[64];
524 readReq->reset(addr, sizeof(T), flags);
526 // translate to physical address - This might be an ISA impl call
527 Fault fault = translateDataReadReq(readReq);
529 // do functional access
530 if (fault == No_Fault)
531 fault = xc->mem->read(readReq, data);
534 traceData->setAddr(addr);
535 if (fault == No_Fault)
536 traceData->setData(data);
540 // if we have a cache, do cache access too
541 if (fault == No_Fault && dcacheInterface) {
543 readReq->completionEvent = NULL;
544 readReq->time = curTick;
545 /*MemAccessResult result = */dcacheInterface->access(readReq);
547 if (dcacheInterface->doEvents()) {
548 readReq->completionEvent = new DCacheCompletionEvent(this, inst);
549 lastDcacheStall = curTick;
550 unscheduleTickEvent();
551 _status = DcacheMissStall;
555 if (!dcacheInterface && (readReq->flags & UNCACHEABLE))
556 recordEvent("Uncached Read");
561 template <class Impl>
564 OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
565 uint64_t *res, DynInstPtr inst)
567 MemReqPtr writeReq = new MemReq();
570 writeReq->data = new uint8_t[64];
574 traceData->setAddr(addr);
575 traceData->setData(data);
579 writeReq->reset(addr, sizeof(T), flags);
581 // translate to physical address
582 Fault fault = xc->translateDataWriteReq(writeReq);
584 // do functional access
585 if (fault == No_Fault)
586 fault = xc->write(writeReq, data);
588 if (fault == No_Fault && dcacheInterface) {
589 writeReq->cmd = Write;
590 memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
591 writeReq->completionEvent = NULL;
592 writeReq->time = curTick;
593 /*MemAccessResult result = */dcacheInterface->access(writeReq);
595 if (dcacheInterface->doEvents()) {
596 writeReq->completionEvent = new DCacheCompletionEvent(this, inst);
597 lastDcacheStall = curTick;
598 unscheduleTickEvent();
599 _status = DcacheMissStall;
603 if (res && (fault == No_Fault))
604 *res = writeReq->result;
606 if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))
607 recordEvent("Uncached Write");
613 #endif // __CPU_OOO_CPU_OOO_CPU_HH__