2 * Copyright (c) 2005 The Regents of The University of Michigan
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29 #ifndef __CPU_OOO_CPU_OOO_CPU_HH__
30 #define __CPU_OOO_CPU_OOO_CPU_HH__
32 #include "base/statistics.hh"
33 #include "config/full_system.hh"
34 #include "cpu/base.hh"
35 #include "cpu/exec_context.hh"
36 #include "encumbered/cpu/full/fu_pool.hh"
37 #include "cpu/ooo_cpu/ea_list.hh"
38 #include "cpu/pc_event.hh"
39 #include "cpu/static_inst.hh"
40 #include "mem/mem_interface.hh"
41 #include "sim/eventq.hh"
43 // forward declarations
67 * Declaration of Out-of-Order CPU class. Basically it is a SimpleCPU with
68 * simple out-of-order capabilities added to it. It is still a 1 CPI machine
69 * (?), but is capable of handling cache misses. Basically it models having
70 * a ROB/IQ by only allowing a certain amount of instructions to execute while
71 * the cache miss is outstanding.
75 class OoOCPU : public BaseCPU
78 typedef typename Impl::DynInst DynInst;
79 typedef typename Impl::DynInstPtr DynInstPtr;
82 // main simulation loop (one cycle)
86 struct TickEvent : public Event
91 TickEvent(OoOCPU *c, int w);
93 const char *description();
98 /// Schedule tick event, regardless of its current state.
99 void scheduleTickEvent(int delay)
101 if (tickEvent.squashed())
102 tickEvent.reschedule(curTick + delay);
103 else if (!tickEvent.scheduled())
104 tickEvent.schedule(curTick + delay);
107 /// Unschedule tick event, regardless of its current state.
108 void unscheduleTickEvent()
110 if (tickEvent.scheduled())
115 Trace::InstRecord *traceData;
118 void trace_data(T data);
135 void post_interrupt(int int_num, int index);
137 void zero_fill_64(Addr addr) {
138 static int warned = 0;
140 warn ("WH64 is not implemented");
145 struct Params : public BaseCPU::Params
147 MemInterface *icache_interface;
148 MemInterface *dcache_interface;
153 FunctionalMemory *mem;
160 OoOCPU(Params *params);
174 void takeOverFrom(BaseCPU *oldCPU);
177 Addr dbg_vtophys(Addr addr);
182 // L1 instruction cache
183 MemInterface *icacheInterface;
186 MemInterface *dcacheInterface;
188 FuncUnitPool *fuPool;
190 // Refcounted pointer to the one memory request.
191 MemReqPtr cacheMemReq;
193 class ICacheCompletionEvent : public Event
199 ICacheCompletionEvent(OoOCPU *_cpu);
201 virtual void process();
202 virtual const char *description();
205 // Will need to create a cache completion event upon any memory miss.
206 ICacheCompletionEvent iCacheCompletionEvent;
208 class DCacheCompletionEvent;
211 std::list<DCacheCompletionEvent>::iterator DCacheCompEventIt;
213 class DCacheCompletionEvent : public Event
218 DCacheCompEventIt dcceIt;
221 DCacheCompletionEvent(OoOCPU *_cpu, DynInstPtr &_inst,
222 DCacheCompEventIt &_dcceIt);
224 virtual void process();
225 virtual const char *description();
228 friend class DCacheCompletionEvent;
231 std::list<DCacheCompletionEvent> dCacheCompList;
232 DCacheCompEventIt dcceIt;
235 Status status() const { return _status; }
237 virtual void activateContext(int thread_num, int delay);
238 virtual void suspendContext(int thread_num);
239 virtual void deallocateContext(int thread_num);
240 virtual void haltContext(int thread_num);
243 virtual void regStats();
244 virtual void resetStats();
246 // number of simulated instructions
248 Counter startNumInst;
249 Stats::Scalar<> numInsts;
251 virtual Counter totalInstructions() const
253 return numInst - startNumInst;
256 // number of simulated memory references
257 Stats::Scalar<> numMemRefs;
259 // number of simulated loads
261 Counter startNumLoad;
263 // number of idle cycles
264 Stats::Average<> notIdleFraction;
265 Stats::Formula idleFraction;
267 // number of cycles stalled for I-cache misses
268 Stats::Scalar<> icacheStallCycles;
269 Counter lastIcacheStall;
271 // number of cycles stalled for D-cache misses
272 Stats::Scalar<> dcacheStallCycles;
273 Counter lastDcacheStall;
275 void processICacheCompletion();
279 virtual void serialize(std::ostream &os);
280 virtual void unserialize(Checkpoint *cp, const std::string §ion);
283 bool validInstAddr(Addr addr) { return true; }
284 bool validDataAddr(Addr addr) { return true; }
285 int getInstAsid() { return xc->regs.instAsid(); }
286 int getDataAsid() { return xc->regs.dataAsid(); }
288 Fault translateInstReq(MemReqPtr &req)
290 return itb->translate(req);
293 Fault translateDataReadReq(MemReqPtr &req)
295 return dtb->translate(req, false);
298 Fault translateDataWriteReq(MemReqPtr &req)
300 return dtb->translate(req, true);
304 bool validInstAddr(Addr addr)
305 { return xc->validInstAddr(addr); }
307 bool validDataAddr(Addr addr)
308 { return xc->validDataAddr(addr); }
310 int getInstAsid() { return xc->asid; }
311 int getDataAsid() { return xc->asid; }
313 Fault dummyTranslation(MemReqPtr &req)
316 assert((req->vaddr >> 48 & 0xffff) == 0);
319 // put the asid in the upper 16 bits of the paddr
320 req->paddr = req->vaddr & ~((Addr)0xffff << sizeof(Addr) * 8 - 16);
321 req->paddr = req->paddr | (Addr)req->asid << sizeof(Addr) * 8 - 16;
324 Fault translateInstReq(MemReqPtr &req)
326 return dummyTranslation(req);
328 Fault translateDataReadReq(MemReqPtr &req)
330 return dummyTranslation(req);
332 Fault translateDataWriteReq(MemReqPtr &req)
334 return dummyTranslation(req);
340 Fault read(Addr addr, T &data, unsigned flags, DynInstPtr inst);
343 Fault write(T data, Addr addr, unsigned flags,
344 uint64_t *res, DynInstPtr inst);
346 void prefetch(Addr addr, unsigned flags)
348 // need to do this...
351 void writeHint(Addr addr, int size, unsigned flags)
353 // need to do this...
356 Fault copySrcTranslate(Addr src);
358 Fault copy(Addr dest);
361 bool executeInst(DynInstPtr &inst);
363 void renameInst(DynInstPtr &inst);
365 void addInst(DynInstPtr &inst);
367 void commitHeadInst();
371 Fault fetchCacheLine();
373 InstSeqNum getAndIncrementInstSeq();
378 InstSeqNum globalSeqNum;
380 DynInstPtr renameTable[TheISA::TotalNumRegs];
381 DynInstPtr commitTable[TheISA::TotalNumRegs];
383 // Might need a table of the shadow registers as well.
385 DynInstPtr palShadowTable[TheISA::NumIntRegs];
389 // The register accessor methods provide the index of the
390 // instruction's operand (e.g., 0 or 1), not the architectural
391 // register index, to simplify the implementation of register
392 // renaming. We find the architectural register index by indexing
393 // into the instruction's own operand index table. Note that a
394 // raw pointer to the StaticInst is provided instead of a
395 // ref-counted StaticInstPtr to redice overhead. This is fine as
396 // long as these methods don't copy the pointer into any long-term
397 // storage (which is pretty hard to imagine they would have reason
400 // In the OoO case these shouldn't read from the XC but rather from the
401 // rename table of DynInsts. Also these likely shouldn't be called very
402 // often, other than when adding things into the xc during say a syscall.
404 uint64_t readIntReg(StaticInst *si, int idx)
406 return xc->readIntReg(si->srcRegIdx(idx));
409 float readFloatRegSingle(StaticInst *si, int idx)
411 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
412 return xc->readFloatRegSingle(reg_idx);
415 double readFloatRegDouble(StaticInst *si, int idx)
417 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
418 return xc->readFloatRegDouble(reg_idx);
421 uint64_t readFloatRegInt(StaticInst *si, int idx)
423 int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
424 return xc->readFloatRegInt(reg_idx);
427 void setIntReg(StaticInst *si, int idx, uint64_t val)
429 xc->setIntReg(si->destRegIdx(idx), val);
432 void setFloatRegSingle(StaticInst *si, int idx, float val)
434 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
435 xc->setFloatRegSingle(reg_idx, val);
438 void setFloatRegDouble(StaticInst *si, int idx, double val)
440 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
441 xc->setFloatRegDouble(reg_idx, val);
444 void setFloatRegInt(StaticInst *si, int idx, uint64_t val)
446 int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
447 xc->setFloatRegInt(reg_idx, val);
450 uint64_t readPC() { return PC; }
451 void setNextPC(Addr val) { nextPC = val; }
460 bool fetchRedirBranch;
462 /** Mask to get a cache block's address. */
465 unsigned cacheBlkSize;
469 /** The cache line being fetched. */
477 // Align an address (typically a PC) to the start of an I-cache block.
478 // We fold in the PISA 64- to 32-bit conversion here as well.
479 Addr icacheBlockAlignPC(Addr addr)
481 addr = TheISA::realPCToFetchPC(addr);
482 return (addr & ~(cacheBlkMask));
487 // ROB tracking stuff.
488 DynInstPtr robHeadPtr;
489 DynInstPtr robTailPtr;
493 // List of outstanding EA instructions.
498 void branchToTarget(Addr val)
500 if (!fetchRedirExcp) {
501 fetchRedirBranch = true;
507 uint64_t readUniq() { return xc->readUniq(); }
508 void setUniq(uint64_t val) { xc->setUniq(val); }
510 uint64_t readFpcr() { return xc->readFpcr(); }
511 void setFpcr(uint64_t val) { xc->setFpcr(val); }
514 uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
515 Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
516 Fault hwrei() { return xc->hwrei(); }
517 int readIntrFlag() { return xc->readIntrFlag(); }
518 void setIntrFlag(int val) { xc->setIntrFlag(val); }
519 bool inPalMode() { return xc->inPalMode(); }
520 void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
521 bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
523 void syscall() { xc->syscall(); }
526 ExecContext *xcBase() { return xc; }
530 // precise architected memory state accessor macros
531 template <class Impl>
534 OoOCPU<Impl>::read(Addr addr, T &data, unsigned flags, DynInstPtr inst)
536 MemReqPtr readReq = new MemReq();
539 readReq->data = new uint8_t[64];
541 readReq->reset(addr, sizeof(T), flags);
543 // translate to physical address - This might be an ISA impl call
544 Fault fault = translateDataReadReq(readReq);
546 // do functional access
547 if (fault == NoFault)
548 fault = xc->mem->read(readReq, data);
551 traceData->setAddr(addr);
552 if (fault == NoFault)
553 traceData->setData(data);
557 // if we have a cache, do cache access too
558 if (fault == NoFault && dcacheInterface) {
560 readReq->completionEvent = NULL;
561 readReq->time = curTick;
562 /*MemAccessResult result = */dcacheInterface->access(readReq);
564 if (dcacheInterface->doEvents()) {
565 readReq->completionEvent = new DCacheCompletionEvent(this, inst,
570 if (!dcacheInterface && (readReq->flags & UNCACHEABLE))
571 recordEvent("Uncached Read");
576 template <class Impl>
579 OoOCPU<Impl>::write(T data, Addr addr, unsigned flags,
580 uint64_t *res, DynInstPtr inst)
582 MemReqPtr writeReq = new MemReq();
585 writeReq->data = new uint8_t[64];
589 traceData->setAddr(addr);
590 traceData->setData(data);
594 writeReq->reset(addr, sizeof(T), flags);
596 // translate to physical address
597 Fault fault = translateDataWriteReq(writeReq);
599 // do functional access
600 if (fault == NoFault)
601 fault = xc->write(writeReq, data);
603 if (fault == NoFault && dcacheInterface) {
604 writeReq->cmd = Write;
605 memcpy(writeReq->data,(uint8_t *)&data,writeReq->size);
606 writeReq->completionEvent = NULL;
607 writeReq->time = curTick;
608 /*MemAccessResult result = */dcacheInterface->access(writeReq);
610 if (dcacheInterface->doEvents()) {
611 writeReq->completionEvent = new DCacheCompletionEvent(this, inst,
616 if (res && (fault == NoFault))
617 *res = writeReq->result;
619 if (!dcacheInterface && (writeReq->flags & UNCACHEABLE))
620 recordEvent("Uncached Write");
626 #endif // __CPU_OOO_CPU_OOO_CPU_HH__