cpu/ozone/cpu_builder.cc

   1
   2 #include <string>
   3
   4 #include "cpu/inst_seq.hh"
   5 #include "cpu/ozone/cpu.hh"
   6 #include "cpu/ozone/ozone_impl.hh"
   7 #include "cpu/ozone/simple_impl.hh"
   8 #include "cpu/ozone/simple_params.hh"
   9 #include "mem/cache/base_cache.hh"
  10 #include "sim/builder.hh"
  11 #include "sim/process.hh"
  12 #include "sim/sim_object.hh"
  13
  14 class DerivOzoneCPU : public OzoneCPU<OzoneImpl>
  15 {
  16   public:
  17     DerivOzoneCPU(SimpleParams *p)
  18         : OzoneCPU<OzoneImpl>(p)
  19     { }
  20 };
  21
  22 class SimpleOzoneCPU : public OzoneCPU<SimpleImpl>
  23 {
  24   public:
  25     SimpleOzoneCPU(SimpleParams *p)
  26         : OzoneCPU<SimpleImpl>(p)
  27     { }
  28 };
  29
  30
  31 ////////////////////////////////////////////////////////////////////////
  32 //
  33 //  OzoneCPU Simulation Object
  34 //
  35
  36 BEGIN_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
  37
  38     Param<int> clock;
  39     Param<int> numThreads;
  40
  41 #if FULL_SYSTEM
  42 SimObjectParam<System *> system;
  43 Param<int> cpu_id;
  44 SimObjectParam<AlphaITB *> itb;
  45 SimObjectParam<AlphaDTB *> dtb;
  46 #else
  47 SimObjectVectorParam<Process *> workload;
  48 //SimObjectParam<PageTable *> page_table;
  49 #endif // FULL_SYSTEM
  50
  51 SimObjectParam<FunctionalMemory *> mem;
  52
  53 Param<Counter> max_insts_any_thread;
  54 Param<Counter> max_insts_all_threads;
  55 Param<Counter> max_loads_any_thread;
  56 Param<Counter> max_loads_all_threads;
  57
  58 SimObjectParam<BaseCache *> icache;
  59 SimObjectParam<BaseCache *> dcache;
  60
  61 Param<unsigned> cachePorts;
  62 Param<unsigned> width;
  63 Param<unsigned> frontEndWidth;
  64 Param<unsigned> backEndWidth;
  65 Param<unsigned> backEndSquashLatency;
  66 Param<unsigned> backEndLatency;
  67 Param<unsigned> maxInstBufferSize;
  68 Param<unsigned> numPhysicalRegs;
  69
  70 Param<unsigned> decodeToFetchDelay;
  71 Param<unsigned> renameToFetchDelay;
  72 Param<unsigned> iewToFetchDelay;
  73 Param<unsigned> commitToFetchDelay;
  74 Param<unsigned> fetchWidth;
  75
  76 Param<unsigned> renameToDecodeDelay;
  77 Param<unsigned> iewToDecodeDelay;
  78 Param<unsigned> commitToDecodeDelay;
  79 Param<unsigned> fetchToDecodeDelay;
  80 Param<unsigned> decodeWidth;
  81
  82 Param<unsigned> iewToRenameDelay;
  83 Param<unsigned> commitToRenameDelay;
  84 Param<unsigned> decodeToRenameDelay;
  85 Param<unsigned> renameWidth;
  86
  87 Param<unsigned> commitToIEWDelay;
  88 Param<unsigned> renameToIEWDelay;
  89 Param<unsigned> issueToExecuteDelay;
  90 Param<unsigned> issueWidth;
  91 Param<unsigned> executeWidth;
  92 Param<unsigned> executeIntWidth;
  93 Param<unsigned> executeFloatWidth;
  94 Param<unsigned> executeBranchWidth;
  95 Param<unsigned> executeMemoryWidth;
  96
  97 Param<unsigned> iewToCommitDelay;
  98 Param<unsigned> renameToROBDelay;
  99 Param<unsigned> commitWidth;
 100 Param<unsigned> squashWidth;
 101
 102 Param<unsigned> localPredictorSize;
 103 Param<unsigned> localCtrBits;
 104 Param<unsigned> localHistoryTableSize;
 105 Param<unsigned> localHistoryBits;
 106 Param<unsigned> globalPredictorSize;
 107 Param<unsigned> globalCtrBits;
 108 Param<unsigned> globalHistoryBits;
 109 Param<unsigned> choicePredictorSize;
 110 Param<unsigned> choiceCtrBits;
 111
 112 Param<unsigned> BTBEntries;
 113 Param<unsigned> BTBTagSize;
 114
 115 Param<unsigned> RASSize;
 116
 117 Param<unsigned> LQEntries;
 118 Param<unsigned> SQEntries;
 119 Param<unsigned> LFSTSize;
 120 Param<unsigned> SSITSize;
 121
 122 Param<unsigned> numPhysIntRegs;
 123 Param<unsigned> numPhysFloatRegs;
 124 Param<unsigned> numIQEntries;
 125 Param<unsigned> numROBEntries;
 126
 127 Param<bool> decoupledFrontEnd;
 128 Param<int> dispatchWidth;
 129 Param<int> wbWidth;
 130
 131 Param<unsigned> smtNumFetchingThreads;
 132 Param<std::string>   smtFetchPolicy;
 133 Param<std::string>   smtLSQPolicy;
 134 Param<unsigned> smtLSQThreshold;
 135 Param<std::string>   smtIQPolicy;
 136 Param<unsigned> smtIQThreshold;
 137 Param<std::string>   smtROBPolicy;
 138 Param<unsigned> smtROBThreshold;
 139 Param<std::string>   smtCommitPolicy;
 140
 141 Param<unsigned> instShiftAmt;
 142
 143 Param<bool> defer_registration;
 144
 145 Param<bool> function_trace;
 146 Param<Tick> function_trace_start;
 147
 148 END_DECLARE_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 149
 150 BEGIN_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 151
 152     INIT_PARAM(clock, "clock speed"),
 153     INIT_PARAM(numThreads, "number of HW thread contexts"),
 154
 155 #if FULL_SYSTEM
 156     INIT_PARAM(system, "System object"),
 157     INIT_PARAM(cpu_id, "processor ID"),
 158     INIT_PARAM(itb, "Instruction translation buffer"),
 159     INIT_PARAM(dtb, "Data translation buffer"),
 160 #else
 161     INIT_PARAM(workload, "Processes to run"),
 162 //    INIT_PARAM(page_table, "Page table"),
 163 #endif // FULL_SYSTEM
 164
 165     INIT_PARAM_DFLT(mem, "Memory", NULL),
 166
 167     INIT_PARAM_DFLT(max_insts_any_thread,
 168                     "Terminate when any thread reaches this inst count",
 169                     0),
 170     INIT_PARAM_DFLT(max_insts_all_threads,
 171                     "Terminate when all threads have reached"
 172                     "this inst count",
 173                     0),
 174     INIT_PARAM_DFLT(max_loads_any_thread,
 175                     "Terminate when any thread reaches this load count",
 176                     0),
 177     INIT_PARAM_DFLT(max_loads_all_threads,
 178                     "Terminate when all threads have reached this load"
 179                     "count",
 180                     0),
 181
 182     INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 183     INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 184
 185     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 186     INIT_PARAM_DFLT(width, "Width", 1),
 187     INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
 188     INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
 189     INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
 190     INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
 191     INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
 192     INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
 193
 194     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 195     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 196     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 197                "delay"),
 198     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 199     INIT_PARAM(fetchWidth, "Fetch width"),
 200     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 201     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 202                "delay"),
 203     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 204     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 205     INIT_PARAM(decodeWidth, "Decode width"),
 206
 207     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 208                "delay"),
 209     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 210     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 211     INIT_PARAM(renameWidth, "Rename width"),
 212
 213     INIT_PARAM(commitToIEWDelay, "Commit to "
 214                "Issue/Execute/Writeback delay"),
 215     INIT_PARAM(renameToIEWDelay, "Rename to "
 216                "Issue/Execute/Writeback delay"),
 217     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 218                "to the IEW stage)"),
 219     INIT_PARAM(issueWidth, "Issue width"),
 220     INIT_PARAM(executeWidth, "Execute width"),
 221     INIT_PARAM(executeIntWidth, "Integer execute width"),
 222     INIT_PARAM(executeFloatWidth, "Floating point execute width"),
 223     INIT_PARAM(executeBranchWidth, "Branch execute width"),
 224     INIT_PARAM(executeMemoryWidth, "Memory execute width"),
 225
 226     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 227                "delay"),
 228     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 229     INIT_PARAM(commitWidth, "Commit width"),
 230     INIT_PARAM(squashWidth, "Squash width"),
 231
 232     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 233     INIT_PARAM(localCtrBits, "Bits per counter"),
 234     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 235     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 236     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 237     INIT_PARAM(globalCtrBits, "Bits per counter"),
 238     INIT_PARAM(globalHistoryBits, "Bits of history"),
 239     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 240     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 241
 242     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 243     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 244
 245     INIT_PARAM(RASSize, "RAS size"),
 246
 247     INIT_PARAM(LQEntries, "Number of load queue entries"),
 248     INIT_PARAM(SQEntries, "Number of store queue entries"),
 249     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 250     INIT_PARAM(SSITSize, "Store set ID table size"),
 251
 252     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 253     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 254                "registers"),
 255     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 256     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 257
 258     INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
 259     INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
 260     INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
 261
 262     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 263     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 264     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 265     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 266     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 267     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 268     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 269     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 270     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 271
 272     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 273     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 274
 275     INIT_PARAM(function_trace, "Enable function trace"),
 276     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 277
 278 END_INIT_SIM_OBJECT_PARAMS(DerivOzoneCPU)
 279
 280 CREATE_SIM_OBJECT(DerivOzoneCPU)
 281 {
 282     DerivOzoneCPU *cpu;
 283
 284 #if FULL_SYSTEM
 285     // Full-system only supports a single thread for the moment.
 286     int actual_num_threads = 1;
 287 #else
 288     // In non-full-system mode, we infer the number of threads from
 289     // the workload if it's not explicitly specified.
 290     int actual_num_threads =
 291         numThreads.isValid() ? numThreads : workload.size();
 292
 293     if (workload.size() == 0) {
 294         fatal("Must specify at least one workload!");
 295     }
 296
 297 #endif
 298
 299     SimpleParams *params = new SimpleParams;
 300
 301     params->clock = clock;
 302
 303     params->name = getInstanceName();
 304     params->numberOfThreads = actual_num_threads;
 305
 306 #if FULL_SYSTEM
 307     params->system = system;
 308     params->cpu_id = cpu_id;
 309     params->itb = itb;
 310     params->dtb = dtb;
 311 #else
 312     params->workload = workload;
 313 //    params->pTable = page_table;
 314 #endif // FULL_SYSTEM
 315
 316     params->mem = mem;
 317
 318     params->max_insts_any_thread = max_insts_any_thread;
 319     params->max_insts_all_threads = max_insts_all_threads;
 320     params->max_loads_any_thread = max_loads_any_thread;
 321     params->max_loads_all_threads = max_loads_all_threads;
 322
 323     //
 324     // Caches
 325     //
 326     params->icacheInterface = icache ? icache->getInterface() : NULL;
 327     params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
 328     params->cachePorts = cachePorts;
 329
 330     params->width = width;
 331     params->frontEndWidth = frontEndWidth;
 332     params->backEndWidth = backEndWidth;
 333     params->backEndSquashLatency = backEndSquashLatency;
 334     params->backEndLatency = backEndLatency;
 335     params->maxInstBufferSize = maxInstBufferSize;
 336     params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
 337
 338     params->decodeToFetchDelay = decodeToFetchDelay;
 339     params->renameToFetchDelay = renameToFetchDelay;
 340     params->iewToFetchDelay = iewToFetchDelay;
 341     params->commitToFetchDelay = commitToFetchDelay;
 342     params->fetchWidth = fetchWidth;
 343
 344     params->renameToDecodeDelay = renameToDecodeDelay;
 345     params->iewToDecodeDelay = iewToDecodeDelay;
 346     params->commitToDecodeDelay = commitToDecodeDelay;
 347     params->fetchToDecodeDelay = fetchToDecodeDelay;
 348     params->decodeWidth = decodeWidth;
 349
 350     params->iewToRenameDelay = iewToRenameDelay;
 351     params->commitToRenameDelay = commitToRenameDelay;
 352     params->decodeToRenameDelay = decodeToRenameDelay;
 353     params->renameWidth = renameWidth;
 354
 355     params->commitToIEWDelay = commitToIEWDelay;
 356     params->renameToIEWDelay = renameToIEWDelay;
 357     params->issueToExecuteDelay = issueToExecuteDelay;
 358     params->issueWidth = issueWidth;
 359     params->executeWidth = executeWidth;
 360     params->executeIntWidth = executeIntWidth;
 361     params->executeFloatWidth = executeFloatWidth;
 362     params->executeBranchWidth = executeBranchWidth;
 363     params->executeMemoryWidth = executeMemoryWidth;
 364
 365     params->iewToCommitDelay = iewToCommitDelay;
 366     params->renameToROBDelay = renameToROBDelay;
 367     params->commitWidth = commitWidth;
 368     params->squashWidth = squashWidth;
 369
 370
 371     params->localPredictorSize = localPredictorSize;
 372     params->localCtrBits = localCtrBits;
 373     params->localHistoryTableSize = localHistoryTableSize;
 374     params->localHistoryBits = localHistoryBits;
 375     params->globalPredictorSize = globalPredictorSize;
 376     params->globalCtrBits = globalCtrBits;
 377     params->globalHistoryBits = globalHistoryBits;
 378     params->choicePredictorSize = choicePredictorSize;
 379     params->choiceCtrBits = choiceCtrBits;
 380
 381     params->BTBEntries = BTBEntries;
 382     params->BTBTagSize = BTBTagSize;
 383
 384     params->RASSize = RASSize;
 385
 386     params->LQEntries = LQEntries;
 387     params->SQEntries = SQEntries;
 388
 389     params->SSITSize = SSITSize;
 390     params->LFSTSize = LFSTSize;
 391
 392     params->numPhysIntRegs = numPhysIntRegs;
 393     params->numPhysFloatRegs = numPhysFloatRegs;
 394     params->numIQEntries = numIQEntries;
 395     params->numROBEntries = numROBEntries;
 396
 397     params->decoupledFrontEnd = decoupledFrontEnd;
 398     params->dispatchWidth = dispatchWidth;
 399     params->wbWidth = wbWidth;
 400
 401     params->smtNumFetchingThreads = smtNumFetchingThreads;
 402     params->smtFetchPolicy = smtFetchPolicy;
 403     params->smtIQPolicy    = smtIQPolicy;
 404     params->smtLSQPolicy    = smtLSQPolicy;
 405     params->smtLSQThreshold = smtLSQThreshold;
 406     params->smtROBPolicy   = smtROBPolicy;
 407     params->smtROBThreshold = smtROBThreshold;
 408     params->smtCommitPolicy = smtCommitPolicy;
 409
 410     params->instShiftAmt = 2;
 411
 412     params->deferRegistration = defer_registration;
 413
 414     params->functionTrace = function_trace;
 415     params->functionTraceStart = function_trace_start;
 416
 417     cpu = new DerivOzoneCPU(params);
 418
 419     return cpu;
 420 }
 421
 422 REGISTER_SIM_OBJECT("DerivOzoneCPU", DerivOzoneCPU)
 423
 424
 425
 426 ////////////////////////////////////////////////////////////////////////
 427 //
 428 //  OzoneCPU Simulation Object
 429 //
 430
 431 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 432
 433     Param<int> clock;
 434     Param<int> numThreads;
 435
 436 #if FULL_SYSTEM
 437 SimObjectParam<System *> system;
 438 Param<int> cpu_id;
 439 SimObjectParam<AlphaITB *> itb;
 440 SimObjectParam<AlphaDTB *> dtb;
 441 #else
 442 SimObjectVectorParam<Process *> workload;
 443 //SimObjectParam<PageTable *> page_table;
 444 #endif // FULL_SYSTEM
 445
 446 SimObjectParam<FunctionalMemory *> mem;
 447
 448 Param<Counter> max_insts_any_thread;
 449 Param<Counter> max_insts_all_threads;
 450 Param<Counter> max_loads_any_thread;
 451 Param<Counter> max_loads_all_threads;
 452
 453 SimObjectParam<BaseCache *> icache;
 454 SimObjectParam<BaseCache *> dcache;
 455
 456 Param<unsigned> cachePorts;
 457 Param<unsigned> width;
 458 Param<unsigned> frontEndWidth;
 459 Param<unsigned> backEndWidth;
 460 Param<unsigned> backEndSquashLatency;
 461 Param<unsigned> backEndLatency;
 462 Param<unsigned> maxInstBufferSize;
 463 Param<unsigned> numPhysicalRegs;
 464
 465 Param<unsigned> decodeToFetchDelay;
 466 Param<unsigned> renameToFetchDelay;
 467 Param<unsigned> iewToFetchDelay;
 468 Param<unsigned> commitToFetchDelay;
 469 Param<unsigned> fetchWidth;
 470
 471 Param<unsigned> renameToDecodeDelay;
 472 Param<unsigned> iewToDecodeDelay;
 473 Param<unsigned> commitToDecodeDelay;
 474 Param<unsigned> fetchToDecodeDelay;
 475 Param<unsigned> decodeWidth;
 476
 477 Param<unsigned> iewToRenameDelay;
 478 Param<unsigned> commitToRenameDelay;
 479 Param<unsigned> decodeToRenameDelay;
 480 Param<unsigned> renameWidth;
 481
 482 Param<unsigned> commitToIEWDelay;
 483 Param<unsigned> renameToIEWDelay;
 484 Param<unsigned> issueToExecuteDelay;
 485 Param<unsigned> issueWidth;
 486 Param<unsigned> executeWidth;
 487 Param<unsigned> executeIntWidth;
 488 Param<unsigned> executeFloatWidth;
 489 Param<unsigned> executeBranchWidth;
 490 Param<unsigned> executeMemoryWidth;
 491
 492 Param<unsigned> iewToCommitDelay;
 493 Param<unsigned> renameToROBDelay;
 494 Param<unsigned> commitWidth;
 495 Param<unsigned> squashWidth;
 496
 497 Param<unsigned> localPredictorSize;
 498 Param<unsigned> localCtrBits;
 499 Param<unsigned> localHistoryTableSize;
 500 Param<unsigned> localHistoryBits;
 501 Param<unsigned> globalPredictorSize;
 502 Param<unsigned> globalCtrBits;
 503 Param<unsigned> globalHistoryBits;
 504 Param<unsigned> choicePredictorSize;
 505 Param<unsigned> choiceCtrBits;
 506
 507 Param<unsigned> BTBEntries;
 508 Param<unsigned> BTBTagSize;
 509
 510 Param<unsigned> RASSize;
 511
 512 Param<unsigned> LQEntries;
 513 Param<unsigned> SQEntries;
 514 Param<unsigned> LFSTSize;
 515 Param<unsigned> SSITSize;
 516
 517 Param<unsigned> numPhysIntRegs;
 518 Param<unsigned> numPhysFloatRegs;
 519 Param<unsigned> numIQEntries;
 520 Param<unsigned> numROBEntries;
 521
 522 Param<bool> decoupledFrontEnd;
 523 Param<int> dispatchWidth;
 524 Param<int> wbWidth;
 525
 526 Param<unsigned> smtNumFetchingThreads;
 527 Param<std::string>   smtFetchPolicy;
 528 Param<std::string>   smtLSQPolicy;
 529 Param<unsigned> smtLSQThreshold;
 530 Param<std::string>   smtIQPolicy;
 531 Param<unsigned> smtIQThreshold;
 532 Param<std::string>   smtROBPolicy;
 533 Param<unsigned> smtROBThreshold;
 534 Param<std::string>   smtCommitPolicy;
 535
 536 Param<unsigned> instShiftAmt;
 537
 538 Param<bool> defer_registration;
 539
 540 Param<bool> function_trace;
 541 Param<Tick> function_trace_start;
 542
 543 END_DECLARE_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 544
 545 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 546
 547     INIT_PARAM(clock, "clock speed"),
 548     INIT_PARAM(numThreads, "number of HW thread contexts"),
 549
 550 #if FULL_SYSTEM
 551     INIT_PARAM(system, "System object"),
 552     INIT_PARAM(cpu_id, "processor ID"),
 553     INIT_PARAM(itb, "Instruction translation buffer"),
 554     INIT_PARAM(dtb, "Data translation buffer"),
 555 #else
 556     INIT_PARAM(workload, "Processes to run"),
 557 //    INIT_PARAM(page_table, "Page table"),
 558 #endif // FULL_SYSTEM
 559
 560     INIT_PARAM_DFLT(mem, "Memory", NULL),
 561
 562     INIT_PARAM_DFLT(max_insts_any_thread,
 563                     "Terminate when any thread reaches this inst count",
 564                     0),
 565     INIT_PARAM_DFLT(max_insts_all_threads,
 566                     "Terminate when all threads have reached"
 567                     "this inst count",
 568                     0),
 569     INIT_PARAM_DFLT(max_loads_any_thread,
 570                     "Terminate when any thread reaches this load count",
 571                     0),
 572     INIT_PARAM_DFLT(max_loads_all_threads,
 573                     "Terminate when all threads have reached this load"
 574                     "count",
 575                     0),
 576
 577     INIT_PARAM_DFLT(icache, "L1 instruction cache", NULL),
 578     INIT_PARAM_DFLT(dcache, "L1 data cache", NULL),
 579
 580     INIT_PARAM_DFLT(cachePorts, "Cache Ports", 200),
 581     INIT_PARAM_DFLT(width, "Width", 1),
 582     INIT_PARAM_DFLT(frontEndWidth, "Front end width", 1),
 583     INIT_PARAM_DFLT(backEndWidth, "Back end width", 1),
 584     INIT_PARAM_DFLT(backEndSquashLatency, "Back end squash latency", 1),
 585     INIT_PARAM_DFLT(backEndLatency, "Back end latency", 1),
 586     INIT_PARAM_DFLT(maxInstBufferSize, "Maximum instruction buffer size", 16),
 587     INIT_PARAM(numPhysicalRegs, "Number of physical registers"),
 588
 589     INIT_PARAM(decodeToFetchDelay, "Decode to fetch delay"),
 590     INIT_PARAM(renameToFetchDelay, "Rename to fetch delay"),
 591     INIT_PARAM(iewToFetchDelay, "Issue/Execute/Writeback to fetch"
 592                "delay"),
 593     INIT_PARAM(commitToFetchDelay, "Commit to fetch delay"),
 594     INIT_PARAM(fetchWidth, "Fetch width"),
 595     INIT_PARAM(renameToDecodeDelay, "Rename to decode delay"),
 596     INIT_PARAM(iewToDecodeDelay, "Issue/Execute/Writeback to decode"
 597                "delay"),
 598     INIT_PARAM(commitToDecodeDelay, "Commit to decode delay"),
 599     INIT_PARAM(fetchToDecodeDelay, "Fetch to decode delay"),
 600     INIT_PARAM(decodeWidth, "Decode width"),
 601
 602     INIT_PARAM(iewToRenameDelay, "Issue/Execute/Writeback to rename"
 603                "delay"),
 604     INIT_PARAM(commitToRenameDelay, "Commit to rename delay"),
 605     INIT_PARAM(decodeToRenameDelay, "Decode to rename delay"),
 606     INIT_PARAM(renameWidth, "Rename width"),
 607
 608     INIT_PARAM(commitToIEWDelay, "Commit to "
 609                "Issue/Execute/Writeback delay"),
 610     INIT_PARAM(renameToIEWDelay, "Rename to "
 611                "Issue/Execute/Writeback delay"),
 612     INIT_PARAM(issueToExecuteDelay, "Issue to execute delay (internal"
 613                "to the IEW stage)"),
 614     INIT_PARAM(issueWidth, "Issue width"),
 615     INIT_PARAM(executeWidth, "Execute width"),
 616     INIT_PARAM(executeIntWidth, "Integer execute width"),
 617     INIT_PARAM(executeFloatWidth, "Floating point execute width"),
 618     INIT_PARAM(executeBranchWidth, "Branch execute width"),
 619     INIT_PARAM(executeMemoryWidth, "Memory execute width"),
 620
 621     INIT_PARAM(iewToCommitDelay, "Issue/Execute/Writeback to commit "
 622                "delay"),
 623     INIT_PARAM(renameToROBDelay, "Rename to reorder buffer delay"),
 624     INIT_PARAM(commitWidth, "Commit width"),
 625     INIT_PARAM(squashWidth, "Squash width"),
 626
 627     INIT_PARAM(localPredictorSize, "Size of local predictor"),
 628     INIT_PARAM(localCtrBits, "Bits per counter"),
 629     INIT_PARAM(localHistoryTableSize, "Size of local history table"),
 630     INIT_PARAM(localHistoryBits, "Bits for the local history"),
 631     INIT_PARAM(globalPredictorSize, "Size of global predictor"),
 632     INIT_PARAM(globalCtrBits, "Bits per counter"),
 633     INIT_PARAM(globalHistoryBits, "Bits of history"),
 634     INIT_PARAM(choicePredictorSize, "Size of choice predictor"),
 635     INIT_PARAM(choiceCtrBits, "Bits of choice counters"),
 636
 637     INIT_PARAM(BTBEntries, "Number of BTB entries"),
 638     INIT_PARAM(BTBTagSize, "Size of the BTB tags, in bits"),
 639
 640     INIT_PARAM(RASSize, "RAS size"),
 641
 642     INIT_PARAM(LQEntries, "Number of load queue entries"),
 643     INIT_PARAM(SQEntries, "Number of store queue entries"),
 644     INIT_PARAM(LFSTSize, "Last fetched store table size"),
 645     INIT_PARAM(SSITSize, "Store set ID table size"),
 646
 647     INIT_PARAM(numPhysIntRegs, "Number of physical integer registers"),
 648     INIT_PARAM(numPhysFloatRegs, "Number of physical floating point "
 649                "registers"),
 650     INIT_PARAM(numIQEntries, "Number of instruction queue entries"),
 651     INIT_PARAM(numROBEntries, "Number of reorder buffer entries"),
 652
 653     INIT_PARAM_DFLT(decoupledFrontEnd, "Decoupled front end", true),
 654     INIT_PARAM_DFLT(dispatchWidth, "Dispatch width", 0),
 655     INIT_PARAM_DFLT(wbWidth, "Writeback width", 0),
 656
 657     INIT_PARAM_DFLT(smtNumFetchingThreads, "SMT Number of Fetching Threads", 1),
 658     INIT_PARAM_DFLT(smtFetchPolicy, "SMT Fetch Policy", "SingleThread"),
 659     INIT_PARAM_DFLT(smtLSQPolicy,   "SMT LSQ Sharing Policy",    "Partitioned"),
 660     INIT_PARAM_DFLT(smtLSQThreshold,"SMT LSQ Threshold", 100),
 661     INIT_PARAM_DFLT(smtIQPolicy,    "SMT IQ Policy",    "Partitioned"),
 662     INIT_PARAM_DFLT(smtIQThreshold, "SMT IQ Threshold", 100),
 663     INIT_PARAM_DFLT(smtROBPolicy,   "SMT ROB Sharing Policy", "Partitioned"),
 664     INIT_PARAM_DFLT(smtROBThreshold,"SMT ROB Threshold", 100),
 665     INIT_PARAM_DFLT(smtCommitPolicy,"SMT Commit Fetch Policy", "RoundRobin"),
 666
 667     INIT_PARAM(instShiftAmt, "Number of bits to shift instructions by"),
 668     INIT_PARAM(defer_registration, "defer system registration (for sampling)"),
 669
 670     INIT_PARAM(function_trace, "Enable function trace"),
 671     INIT_PARAM(function_trace_start, "Cycle to start function trace")
 672
 673 END_INIT_SIM_OBJECT_PARAMS(SimpleOzoneCPU)
 674
 675 CREATE_SIM_OBJECT(SimpleOzoneCPU)
 676 {
 677     SimpleOzoneCPU *cpu;
 678
 679 #if FULL_SYSTEM
 680     // Full-system only supports a single thread for the moment.
 681     int actual_num_threads = 1;
 682 #else
 683     // In non-full-system mode, we infer the number of threads from
 684     // the workload if it's not explicitly specified.
 685     int actual_num_threads =
 686         numThreads.isValid() ? numThreads : workload.size();
 687
 688     if (workload.size() == 0) {
 689         fatal("Must specify at least one workload!");
 690     }
 691
 692 #endif
 693
 694     SimpleParams *params = new SimpleParams;
 695
 696     params->clock = clock;
 697
 698     params->name = getInstanceName();
 699     params->numberOfThreads = actual_num_threads;
 700
 701 #if FULL_SYSTEM
 702     params->system = system;
 703     params->cpu_id = cpu_id;
 704     params->itb = itb;
 705     params->dtb = dtb;
 706 #else
 707     params->workload = workload;
 708 //    params->pTable = page_table;
 709 #endif // FULL_SYSTEM
 710
 711     params->mem = mem;
 712
 713     params->max_insts_any_thread = max_insts_any_thread;
 714     params->max_insts_all_threads = max_insts_all_threads;
 715     params->max_loads_any_thread = max_loads_any_thread;
 716     params->max_loads_all_threads = max_loads_all_threads;
 717
 718     //
 719     // Caches
 720     //
 721     params->icacheInterface = icache ? icache->getInterface() : NULL;
 722     params->dcacheInterface = dcache ? dcache->getInterface() : NULL;
 723     params->cachePorts = cachePorts;
 724
 725     params->width = width;
 726     params->frontEndWidth = frontEndWidth;
 727     params->backEndWidth = backEndWidth;
 728     params->backEndSquashLatency = backEndSquashLatency;
 729     params->backEndLatency = backEndLatency;
 730     params->maxInstBufferSize = maxInstBufferSize;
 731     params->numPhysicalRegs = numPhysIntRegs + numPhysFloatRegs;
 732
 733     params->decodeToFetchDelay = decodeToFetchDelay;
 734     params->renameToFetchDelay = renameToFetchDelay;
 735     params->iewToFetchDelay = iewToFetchDelay;
 736     params->commitToFetchDelay = commitToFetchDelay;
 737     params->fetchWidth = fetchWidth;
 738
 739     params->renameToDecodeDelay = renameToDecodeDelay;
 740     params->iewToDecodeDelay = iewToDecodeDelay;
 741     params->commitToDecodeDelay = commitToDecodeDelay;
 742     params->fetchToDecodeDelay = fetchToDecodeDelay;
 743     params->decodeWidth = decodeWidth;
 744
 745     params->iewToRenameDelay = iewToRenameDelay;
 746     params->commitToRenameDelay = commitToRenameDelay;
 747     params->decodeToRenameDelay = decodeToRenameDelay;
 748     params->renameWidth = renameWidth;
 749
 750     params->commitToIEWDelay = commitToIEWDelay;
 751     params->renameToIEWDelay = renameToIEWDelay;
 752     params->issueToExecuteDelay = issueToExecuteDelay;
 753     params->issueWidth = issueWidth;
 754     params->executeWidth = executeWidth;
 755     params->executeIntWidth = executeIntWidth;
 756     params->executeFloatWidth = executeFloatWidth;
 757     params->executeBranchWidth = executeBranchWidth;
 758     params->executeMemoryWidth = executeMemoryWidth;
 759
 760     params->iewToCommitDelay = iewToCommitDelay;
 761     params->renameToROBDelay = renameToROBDelay;
 762     params->commitWidth = commitWidth;
 763     params->squashWidth = squashWidth;
 764
 765
 766     params->localPredictorSize = localPredictorSize;
 767     params->localCtrBits = localCtrBits;
 768     params->localHistoryTableSize = localHistoryTableSize;
 769     params->localHistoryBits = localHistoryBits;
 770     params->globalPredictorSize = globalPredictorSize;
 771     params->globalCtrBits = globalCtrBits;
 772     params->globalHistoryBits = globalHistoryBits;
 773     params->choicePredictorSize = choicePredictorSize;
 774     params->choiceCtrBits = choiceCtrBits;
 775
 776     params->BTBEntries = BTBEntries;
 777     params->BTBTagSize = BTBTagSize;
 778
 779     params->RASSize = RASSize;
 780
 781     params->LQEntries = LQEntries;
 782     params->SQEntries = SQEntries;
 783
 784     params->SSITSize = SSITSize;
 785     params->LFSTSize = LFSTSize;
 786
 787     params->numPhysIntRegs = numPhysIntRegs;
 788     params->numPhysFloatRegs = numPhysFloatRegs;
 789     params->numIQEntries = numIQEntries;
 790     params->numROBEntries = numROBEntries;
 791
 792     params->decoupledFrontEnd = decoupledFrontEnd;
 793     params->dispatchWidth = dispatchWidth;
 794     params->wbWidth = wbWidth;
 795
 796     params->smtNumFetchingThreads = smtNumFetchingThreads;
 797     params->smtFetchPolicy = smtFetchPolicy;
 798     params->smtIQPolicy    = smtIQPolicy;
 799     params->smtLSQPolicy    = smtLSQPolicy;
 800     params->smtLSQThreshold = smtLSQThreshold;
 801     params->smtROBPolicy   = smtROBPolicy;
 802     params->smtROBThreshold = smtROBThreshold;
 803     params->smtCommitPolicy = smtCommitPolicy;
 804
 805     params->instShiftAmt = 2;
 806
 807     params->deferRegistration = defer_registration;
 808
 809     params->functionTrace = function_trace;
 810     params->functionTraceStart = function_trace_start;
 811
 812     cpu = new SimpleOzoneCPU(params);
 813
 814     return cpu;
 815 }
 816
 817 REGISTER_SIM_OBJECT("SimpleOzoneCPU", SimpleOzoneCPU)
 818