cpu/simple/atomic.hh

   1 /*
   2  * Copyright (c) 2002-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_SIMPLE_ATOMIC_HH__
  30 #define __CPU_SIMPLE_ATOMIC_HH__
  31
  32 #include "cpu/simple/base.hh"
  33
  34 class AtomicSimpleCPU : public BaseSimpleCPU
  35 {
  36   public:
  37
  38     struct Params : public BaseSimpleCPU::Params {
  39         int width;
  40         bool simulate_stalls;
  41     };
  42
  43     AtomicSimpleCPU(Params *params);
  44     virtual ~AtomicSimpleCPU();
  45
  46     virtual void init();
  47
  48   public:
  49     //
  50     enum Status {
  51         Running,
  52         Idle,
  53         SwitchedOut
  54     };
  55
  56   protected:
  57     Status _status;
  58
  59     Status status() const { return _status; }
  60
  61   private:
  62
  63     struct TickEvent : public Event
  64     {
  65         AtomicSimpleCPU *cpu;
  66
  67         TickEvent(AtomicSimpleCPU *c);
  68         void process();
  69         const char *description();
  70     };
  71
  72     TickEvent tickEvent;
  73
  74     const int width;
  75     const bool simulate_stalls;
  76
  77     // main simulation loop (one cycle)
  78     void tick();
  79
  80     class CpuPort : public Port
  81     {
  82
  83         AtomicSimpleCPU *cpu;
  84
  85       public:
  86
  87         CpuPort(AtomicSimpleCPU *_cpu)
  88             : cpu(_cpu)
  89         { }
  90
  91       protected:
  92
  93         virtual bool recvTiming(Packet *pkt);
  94
  95         virtual Tick recvAtomic(Packet *pkt);
  96
  97         virtual void recvFunctional(Packet *pkt);
  98
  99         virtual void recvStatusChange(Status status);
 100
 101         virtual Packet *recvRetry();
 102
 103         virtual void getDeviceAddressRanges(AddrRangeList &resp,
 104             AddrRangeList &snoop)
 105         { resp.clear(); snoop.clear(); }
 106     };
 107
 108     CpuPort icachePort;
 109     CpuPort dcachePort;
 110
 111     Request *ifetch_req;
 112     Packet  *ifetch_pkt;
 113     Request *data_read_req;
 114     Packet  *data_read_pkt;
 115     Request *data_write_req;
 116     Packet  *data_write_pkt;
 117
 118     bool dcache_access;
 119     Tick dcache_complete;
 120
 121   public:
 122
 123     virtual void serialize(std::ostream &os);
 124     virtual void unserialize(Checkpoint *cp, const std::string &section);
 125
 126     void switchOut(Sampler *s);
 127     void takeOverFrom(BaseCPU *oldCPU);
 128
 129     virtual void activateContext(int thread_num, int delay);
 130     virtual void suspendContext(int thread_num);
 131
 132     template <class T>
 133     Fault read(Addr addr, T &data, unsigned flags);
 134
 135     template <class T>
 136     Fault write(T data, Addr addr, unsigned flags, uint64_t *res);
 137 };
 138
 139 #endif // __CPU_SIMPLE_ATOMIC_HH__