cpu/simple_cpu/simple_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cmath>
  30 #include <cstdio>
  31 #include <cstdlib>
  32 #include <iostream>
  33 #include <iomanip>
  34 #include <list>
  35 #include <sstream>
  36 #include <string>
  37
  38 #include "base/cprintf.hh"
  39 #include "base/inifile.hh"
  40 #include "base/loader/symtab.hh"
  41 #include "base/misc.hh"
  42 #include "base/pollevent.hh"
  43 #include "base/range.hh"
  44 #include "base/trace.hh"
  45 #include "cpu/base_cpu.hh"
  46 #include "cpu/exec_context.hh"
  47 #include "cpu/exetrace.hh"
  48 #include "cpu/full_cpu/smt.hh"
  49 #include "cpu/simple_cpu/simple_cpu.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "mem/base_mem.hh"
  52 #include "mem/mem_interface.hh"
  53 #include "sim/annotation.hh"
  54 #include "sim/builder.hh"
  55 #include "sim/debug.hh"
  56 #include "sim/host.hh"
  57 #include "sim/sim_events.hh"
  58 #include "sim/sim_object.hh"
  59 #include "sim/sim_stats.hh"
  60
  61 #ifdef FULL_SYSTEM
  62 #include "base/remote_gdb.hh"
  63 #include "dev/alpha_access.h"
  64 #include "dev/pciareg.h"
  65 #include "mem/functional_mem/memory_control.hh"
  66 #include "mem/functional_mem/physical_memory.hh"
  67 #include "sim/system.hh"
  68 #include "targetarch/alpha_memory.hh"
  69 #include "targetarch/vtophys.hh"
  70 #else // !FULL_SYSTEM
  71 #include "eio/eio.hh"
  72 #include "mem/functional_mem/functional_memory.hh"
  73 #endif // FULL_SYSTEM
  74
  75 using namespace std;
  76
  77 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
  78     : Event(&mainEventQueue, 100), cpu(c)
  79 {
  80 }
  81
  82 void
  83 SimpleCPU::TickEvent::process()
  84 {
  85     cpu->tick();
  86 }
  87
  88 const char *
  89 SimpleCPU::TickEvent::description()
  90 {
  91     return "SimpleCPU tick event";
  92 }
  93
  94
  95 SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
  96     : Event(&mainEventQueue),
  97       cpu(_cpu)
  98 {
  99 }
 100
 101 void SimpleCPU::CacheCompletionEvent::process()
 102 {
 103     cpu->processCacheCompletion();
 104 }
 105
 106 const char *
 107 SimpleCPU::CacheCompletionEvent::description()
 108 {
 109     return "SimpleCPU cache completion event";
 110 }
 111
 112 #ifdef FULL_SYSTEM
 113 SimpleCPU::SimpleCPU(const string &_name,
 114                      System *_system,
 115                      Counter max_insts_any_thread,
 116                      Counter max_insts_all_threads,
 117                      Counter max_loads_any_thread,
 118                      Counter max_loads_all_threads,
 119                      AlphaItb *itb, AlphaDtb *dtb,
 120                      FunctionalMemory *mem,
 121                      MemInterface *icache_interface,
 122                      MemInterface *dcache_interface,
 123                      Tick freq)
 124     : BaseCPU(_name, /* number_of_threads */ 1,
 125               max_insts_any_thread, max_insts_all_threads,
 126               max_loads_any_thread, max_loads_all_threads,
 127               _system, freq),
 128 #else
 129 SimpleCPU::SimpleCPU(const string &_name, Process *_process,
 130                      Counter max_insts_any_thread,
 131                      Counter max_insts_all_threads,
 132                      Counter max_loads_any_thread,
 133                      Counter max_loads_all_threads,
 134                      MemInterface *icache_interface,
 135                      MemInterface *dcache_interface)
 136     : BaseCPU(_name, /* number_of_threads */ 1,
 137               max_insts_any_thread, max_insts_all_threads,
 138               max_loads_any_thread, max_loads_all_threads),
 139 #endif
 140       tickEvent(this), xc(NULL), cacheCompletionEvent(this)
 141 {
 142     _status = Idle;
 143 #ifdef FULL_SYSTEM
 144     xc = new ExecContext(this, 0, system, itb, dtb, mem);
 145
 146     // initialize CPU, including PC
 147     TheISA::initCPU(&xc->regs);
 148 #else
 149     xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
 150 #endif // !FULL_SYSTEM
 151
 152     icacheInterface = icache_interface;
 153     dcacheInterface = dcache_interface;
 154
 155     memReq = new MemReq();
 156     memReq->xc = xc;
 157     memReq->asid = 0;
 158     memReq->data = new uint8_t[64];
 159
 160     numInst = 0;
 161     startNumInst = 0;
 162     numLoad = 0;
 163     startNumLoad = 0;
 164     lastIcacheStall = 0;
 165     lastDcacheStall = 0;
 166
 167     execContexts.push_back(xc);
 168 }
 169
 170 SimpleCPU::~SimpleCPU()
 171 {
 172 }
 173
 174 void
 175 SimpleCPU::switchOut()
 176 {
 177     _status = SwitchedOut;
 178     if (tickEvent.scheduled())
 179         tickEvent.squash();
 180 }
 181
 182
 183 void
 184 SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 185 {
 186     BaseCPU::takeOverFrom(oldCPU);
 187
 188     assert(!tickEvent.scheduled());
 189
 190     // if any of this CPU's ExecContexts are active, mark the CPU as
 191     // running and schedule its tick event.
 192     for (int i = 0; i < execContexts.size(); ++i) {
 193         ExecContext *xc = execContexts[i];
 194         if (xc->status() == ExecContext::Active && _status != Running) {
 195             _status = Running;
 196             tickEvent.schedule(curTick);
 197         }
 198     }
 199
 200     oldCPU->switchOut();
 201 }
 202
 203
 204 void
 205 SimpleCPU::execCtxStatusChg(int thread_num) {
 206     assert(thread_num == 0);
 207     assert(xc);
 208
 209     if (xc->status() == ExecContext::Active)
 210         setStatus(Running);
 211     else
 212         setStatus(Idle);
 213 }
 214
 215
 216 void
 217 SimpleCPU::regStats()
 218 {
 219     using namespace Statistics;
 220
 221     BaseCPU::regStats();
 222
 223     numInsts
 224         .name(name() + ".num_insts")
 225         .desc("Number of instructions executed")
 226         ;
 227
 228     numMemRefs
 229         .name(name() + ".num_refs")
 230         .desc("Number of memory references")
 231         ;
 232
 233     idleFraction
 234         .name(name() + ".idle_fraction")
 235         .desc("Percentage of idle cycles")
 236         ;
 237
 238     icacheStallCycles
 239         .name(name() + ".icache_stall_cycles")
 240         .desc("ICache total stall cycles")
 241         .prereq(icacheStallCycles)
 242         ;
 243
 244     dcacheStallCycles
 245         .name(name() + ".dcache_stall_cycles")
 246         .desc("DCache total stall cycles")
 247         .prereq(dcacheStallCycles)
 248         ;
 249
 250     numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
 251     simInsts += numInsts;
 252 }
 253
 254 void
 255 SimpleCPU::resetStats()
 256 {
 257     startNumInst = numInst;
 258 }
 259
 260 void
 261 SimpleCPU::serialize(ostream &os)
 262 {
 263     SERIALIZE_ENUM(_status);
 264     SERIALIZE_SCALAR(inst);
 265     nameOut(os, csprintf("%s.xc", name()));
 266     xc->serialize(os);
 267     nameOut(os, csprintf("%s.tickEvent", name()));
 268     tickEvent.serialize(os);
 269     nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
 270     cacheCompletionEvent.serialize(os);
 271 }
 272
 273 void
 274 SimpleCPU::unserialize(Checkpoint *cp, const string &section)
 275 {
 276     UNSERIALIZE_ENUM(_status);
 277     UNSERIALIZE_SCALAR(inst);
 278     xc->unserialize(cp, csprintf("%s.xc", section));
 279     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 280     cacheCompletionEvent
 281         .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
 282 }
 283
 284 void
 285 change_thread_state(int thread_number, int activate, int priority)
 286 {
 287 }
 288
 289 // precise architected memory state accessor macros
 290 template <class T>
 291 Fault
 292 SimpleCPU::read(Addr addr, T& data, unsigned flags)
 293 {
 294     memReq->reset(addr, sizeof(T), flags);
 295
 296     // translate to physical address
 297     Fault fault = xc->translateDataReadReq(memReq);
 298
 299     // do functional access
 300     if (fault == No_Fault)
 301         fault = xc->read(memReq, data);
 302
 303     if (traceData) {
 304         traceData->setAddr(addr);
 305         if (fault == No_Fault)
 306             traceData->setData(data);
 307     }
 308
 309     // if we have a cache, do cache access too
 310     if (fault == No_Fault && dcacheInterface) {
 311         memReq->cmd = Read;
 312         memReq->completionEvent = NULL;
 313         memReq->time = curTick;
 314         memReq->flags &= ~UNCACHEABLE;
 315         MemAccessResult result = dcacheInterface->access(memReq);
 316
 317         // Ugly hack to get an event scheduled *only* if the access is
 318         // a miss.  We really should add first-class support for this
 319         // at some point.
 320         if (result != MA_HIT && dcacheInterface->doEvents) {
 321             memReq->completionEvent = &cacheCompletionEvent;
 322             setStatus(DcacheMissStall);
 323         }
 324     }
 325
 326     return fault;
 327 }
 328
 329 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 330
 331 template
 332 Fault
 333 SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
 334
 335 template
 336 Fault
 337 SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
 338
 339 template
 340 Fault
 341 SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
 342
 343 template
 344 Fault
 345 SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
 346
 347 #endif //DOXYGEN_SHOULD_SKIP_THIS
 348
 349 template<>
 350 Fault
 351 SimpleCPU::read(Addr addr, double& data, unsigned flags)
 352 {
 353     return read(addr, *(uint64_t*)&data, flags);
 354 }
 355
 356 template<>
 357 Fault
 358 SimpleCPU::read(Addr addr, float& data, unsigned flags)
 359 {
 360     return read(addr, *(uint32_t*)&data, flags);
 361 }
 362
 363
 364 template<>
 365 Fault
 366 SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
 367 {
 368     return read(addr, (uint32_t&)data, flags);
 369 }
 370
 371
 372 template <class T>
 373 Fault
 374 SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 375 {
 376     if (traceData) {
 377         traceData->setAddr(addr);
 378         traceData->setData(data);
 379     }
 380
 381     memReq->reset(addr, sizeof(T), flags);
 382
 383     // translate to physical address
 384     Fault fault = xc->translateDataWriteReq(memReq);
 385
 386     // do functional access
 387     if (fault == No_Fault)
 388         fault = xc->write(memReq, data);
 389
 390     if (fault == No_Fault && dcacheInterface) {
 391         memReq->cmd = Write;
 392         memcpy(memReq->data,(uint8_t *)&data,memReq->size);
 393         memReq->completionEvent = NULL;
 394         memReq->time = curTick;
 395         memReq->flags &= ~UNCACHEABLE;
 396         MemAccessResult result = dcacheInterface->access(memReq);
 397
 398         // Ugly hack to get an event scheduled *only* if the access is
 399         // a miss.  We really should add first-class support for this
 400         // at some point.
 401         if (result != MA_HIT && dcacheInterface->doEvents) {
 402             memReq->completionEvent = &cacheCompletionEvent;
 403             setStatus(DcacheMissStall);
 404         }
 405     }
 406
 407     if (res && (fault == No_Fault))
 408         *res = memReq->result;
 409
 410     return fault;
 411 }
 412
 413
 414 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 415 template
 416 Fault
 417 SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
 418
 419 template
 420 Fault
 421 SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
 422
 423 template
 424 Fault
 425 SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
 426
 427 template
 428 Fault
 429 SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
 430
 431 #endif //DOXYGEN_SHOULD_SKIP_THIS
 432
 433 template<>
 434 Fault
 435 SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 436 {
 437     return write(*(uint64_t*)&data, addr, flags, res);
 438 }
 439
 440 template<>
 441 Fault
 442 SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 443 {
 444     return write(*(uint32_t*)&data, addr, flags, res);
 445 }
 446
 447
 448 template<>
 449 Fault
 450 SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 451 {
 452     return write((uint32_t)data, addr, flags, res);
 453 }
 454
 455
 456 #ifdef FULL_SYSTEM
 457 Addr
 458 SimpleCPU::dbg_vtophys(Addr addr)
 459 {
 460     return vtophys(xc, addr);
 461 }
 462 #endif // FULL_SYSTEM
 463
 464 Tick save_cycle = 0;
 465
 466
 467 void
 468 SimpleCPU::processCacheCompletion()
 469 {
 470     switch (status()) {
 471       case IcacheMissStall:
 472         icacheStallCycles += curTick - lastIcacheStall;
 473         setStatus(IcacheMissComplete);
 474         break;
 475       case DcacheMissStall:
 476         dcacheStallCycles += curTick - lastDcacheStall;
 477         setStatus(Running);
 478         break;
 479       case SwitchedOut:
 480         // If this CPU has been switched out due to sampling/warm-up,
 481         // ignore any further status changes (e.g., due to cache
 482         // misses outstanding at the time of the switch).
 483         return;
 484       default:
 485         panic("SimpleCPU::processCacheCompletion: bad state");
 486         break;
 487     }
 488 }
 489
 490 #ifdef FULL_SYSTEM
 491 void
 492 SimpleCPU::post_interrupt(int int_num, int index)
 493 {
 494     BaseCPU::post_interrupt(int_num, index);
 495
 496     if (xc->status() == ExecContext::Suspended) {
 497                 DPRINTF(IPI,"Suspended Processor awoke\n");
 498         xc->setStatus(ExecContext::Active);
 499         Annotate::Resume(xc);
 500     }
 501 }
 502 #endif // FULL_SYSTEM
 503
 504 /* start simulation, program loaded, processor precise state initialized */
 505 void
 506 SimpleCPU::tick()
 507 {
 508     traceData = NULL;
 509
 510     Fault fault = No_Fault;
 511
 512 #ifdef FULL_SYSTEM
 513     if (AlphaISA::check_interrupts &&
 514         xc->cpu->check_interrupts() &&
 515         !PC_PAL(xc->regs.pc) &&
 516         status() != IcacheMissComplete) {
 517         int ipl = 0;
 518         int summary = 0;
 519         AlphaISA::check_interrupts = 0;
 520         IntReg *ipr = xc->regs.ipr;
 521
 522         if (xc->regs.ipr[TheISA::IPR_SIRR]) {
 523             for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
 524                  i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
 525                 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
 526                     // See table 4-19 of 21164 hardware reference
 527                     ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
 528                     summary |= (ULL(1) << i);
 529                 }
 530             }
 531         }
 532
 533         uint64_t interrupts = xc->cpu->intr_status();
 534         for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
 535             i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
 536             if (interrupts & (ULL(1) << i)) {
 537                 // See table 4-19 of 21164 hardware reference
 538                 ipl = i;
 539                 summary |= (ULL(1) << i);
 540             }
 541         }
 542
 543         if (ipr[TheISA::IPR_ASTRR])
 544             panic("asynchronous traps not implemented\n");
 545
 546         if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
 547             ipr[TheISA::IPR_ISR] = summary;
 548             ipr[TheISA::IPR_INTID] = ipl;
 549             xc->ev5_trap(Interrupt_Fault);
 550
 551             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 552                     ipr[TheISA::IPR_IPLR], ipl, summary);
 553         }
 554     }
 555 #endif
 556
 557     // maintain $r0 semantics
 558     xc->regs.intRegFile[ZeroReg] = 0;
 559 #ifdef TARGET_ALPHA
 560     xc->regs.floatRegFile.d[ZeroReg] = 0.0;
 561 #endif // TARGET_ALPHA
 562
 563     if (status() == IcacheMissComplete) {
 564         // We've already fetched an instruction and were stalled on an
 565         // I-cache miss.  No need to fetch it again.
 566
 567         setStatus(Running);
 568     }
 569     else {
 570         // Try to fetch an instruction
 571
 572         // set up memory request for instruction fetch
 573 #ifdef FULL_SYSTEM
 574 #define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 575 #else
 576 #define IFETCH_FLAGS(pc)        0
 577 #endif
 578
 579         memReq->cmd = Read;
 580         memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
 581                      IFETCH_FLAGS(xc->regs.pc));
 582
 583         fault = xc->translateInstReq(memReq);
 584
 585         if (fault == No_Fault)
 586             fault = xc->mem->read(memReq, inst);
 587
 588         if (icacheInterface && fault == No_Fault) {
 589             memReq->completionEvent = NULL;
 590
 591             memReq->time = curTick;
 592             memReq->flags &= ~UNCACHEABLE;
 593             MemAccessResult result = icacheInterface->access(memReq);
 594
 595             // Ugly hack to get an event scheduled *only* if the access is
 596             // a miss.  We really should add first-class support for this
 597             // at some point.
 598             if (result != MA_HIT && icacheInterface->doEvents) {
 599                 memReq->completionEvent = &cacheCompletionEvent;
 600                 setStatus(IcacheMissStall);
 601                 return;
 602             }
 603         }
 604     }
 605
 606     // If we've got a valid instruction (i.e., no fault on instruction
 607     // fetch), then execute it.
 608     if (fault == No_Fault) {
 609
 610         // keep an instruction count
 611         numInst++;
 612
 613         // check for instruction-count-based events
 614         comInsnEventQueue[0]->serviceEvents(numInst);
 615
 616         // decode the instruction
 617         StaticInstPtr<TheISA> si(inst);
 618
 619         traceData = Trace::getInstRecord(curTick, xc, this, si,
 620                                          xc->regs.pc);
 621
 622 #ifdef FULL_SYSTEM
 623         xc->regs.opcode = (inst >> 26) & 0x3f;
 624         xc->regs.ra = (inst >> 21) & 0x1f;
 625 #endif // FULL_SYSTEM
 626
 627         xc->func_exe_insn++;
 628
 629         fault = si->execute(this, xc, traceData);
 630 #ifdef FS_MEASURE
 631         if (!(xc->misspeculating()) && (xc->system->bin)) {
 632             SWContext *ctx = xc->swCtx;
 633             if (ctx && !ctx->callStack.empty()) {
 634                 if (si->isCall()) {
 635                     ctx->calls++;
 636                 }
 637                 if (si->isReturn()) {
 638                      if (ctx->calls == 0) {
 639                         fnCall *top = ctx->callStack.top();
 640                         DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
 641                         delete top;
 642                         ctx->callStack.pop();
 643                         if (ctx->callStack.empty())
 644                             xc->system->nonPath->activate();
 645                         else
 646                             ctx->callStack.top()->myBin->activate();
 647
 648                         xc->system->dumpState(xc);
 649                     } else {
 650                         ctx->calls--;
 651                     }
 652                 }
 653             }
 654         }
 655 #endif
 656         if (si->isMemRef()) {
 657             numMemRefs++;
 658         }
 659
 660         if (si->isLoad()) {
 661             ++numLoad;
 662             comLoadEventQueue[0]->serviceEvents(numLoad);
 663         }
 664
 665         if (traceData)
 666             traceData->finalize();
 667
 668     }   // if (fault == No_Fault)
 669
 670     if (fault != No_Fault) {
 671 #ifdef FULL_SYSTEM
 672         xc->ev5_trap(fault);
 673 #else // !FULL_SYSTEM
 674         fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
 675 #endif // FULL_SYSTEM
 676     }
 677     else {
 678         // go to the next instruction
 679         xc->regs.pc = xc->regs.npc;
 680         xc->regs.npc += sizeof(MachInst);
 681     }
 682
 683 #ifdef FULL_SYSTEM
 684     Addr oldpc;
 685     do {
 686         oldpc = xc->regs.pc;
 687         system->pcEventQueue.service(xc);
 688     } while (oldpc != xc->regs.pc);
 689 #endif
 690
 691     assert(status() == Running ||
 692            status() == Idle ||
 693            status() == DcacheMissStall);
 694
 695     if (status() == Running && !tickEvent.scheduled())
 696         tickEvent.schedule(curTick + 1);
 697 }
 698
 699
 700 ////////////////////////////////////////////////////////////////////////
 701 //
 702 //  SimpleCPU Simulation Object
 703 //
 704 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 705
 706     Param<Counter> max_insts_any_thread;
 707     Param<Counter> max_insts_all_threads;
 708     Param<Counter> max_loads_any_thread;
 709     Param<Counter> max_loads_all_threads;
 710
 711 #ifdef FULL_SYSTEM
 712     SimObjectParam<AlphaItb *> itb;
 713     SimObjectParam<AlphaDtb *> dtb;
 714     SimObjectParam<FunctionalMemory *> mem;
 715     SimObjectParam<System *> system;
 716     Param<int> mult;
 717 #else
 718     SimObjectParam<Process *> workload;
 719 #endif // FULL_SYSTEM
 720
 721     SimObjectParam<BaseMem *> icache;
 722     SimObjectParam<BaseMem *> dcache;
 723
 724     Param<bool> defer_registration;
 725
 726 END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 727
 728 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 729
 730     INIT_PARAM_DFLT(max_insts_any_thread,
 731                     "terminate when any thread reaches this insn count",
 732                     0),
 733     INIT_PARAM_DFLT(max_insts_all_threads,
 734                     "terminate when all threads have reached this insn count",
 735                     0),
 736     INIT_PARAM_DFLT(max_loads_any_thread,
 737                     "terminate when any thread reaches this load count",
 738                     0),
 739     INIT_PARAM_DFLT(max_loads_all_threads,
 740                     "terminate when all threads have reached this load count",
 741                     0),
 742
 743 #ifdef FULL_SYSTEM
 744     INIT_PARAM(itb, "Instruction TLB"),
 745     INIT_PARAM(dtb, "Data TLB"),
 746     INIT_PARAM(mem, "memory"),
 747     INIT_PARAM(system, "system object"),
 748     INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
 749 #else
 750     INIT_PARAM(workload, "processes to run"),
 751 #endif // FULL_SYSTEM
 752
 753     INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
 754     INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
 755     INIT_PARAM_DFLT(defer_registration, "defer registration with system "
 756                     "(for sampling)", false)
 757
 758 END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 759
 760
 761 CREATE_SIM_OBJECT(SimpleCPU)
 762 {
 763     SimpleCPU *cpu;
 764 #ifdef FULL_SYSTEM
 765     if (mult != 1)
 766         panic("processor clock multiplier must be 1\n");
 767
 768     cpu = new SimpleCPU(getInstanceName(), system,
 769                         max_insts_any_thread, max_insts_all_threads,
 770                         max_loads_any_thread, max_loads_all_threads,
 771                         itb, dtb, mem,
 772                         (icache) ? icache->getInterface() : NULL,
 773                         (dcache) ? dcache->getInterface() : NULL,
 774                         ticksPerSecond * mult);
 775 #else
 776
 777     cpu = new SimpleCPU(getInstanceName(), workload,
 778                         max_insts_any_thread, max_insts_all_threads,
 779                         max_loads_any_thread, max_loads_all_threads,
 780                         (icache) ? icache->getInterface() : NULL,
 781                         (dcache) ? dcache->getInterface() : NULL);
 782
 783 #endif // FULL_SYSTEM
 784
 785     if (!defer_registration) {
 786         cpu->registerExecContexts();
 787     }
 788
 789     return cpu;
 790 }
 791
 792 REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)