2 * Copyright (c) 2003 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
38 #include "base/cprintf.hh"
39 #include "base/inifile.hh"
40 #include "base/loader/symtab.hh"
41 #include "base/misc.hh"
42 #include "base/pollevent.hh"
43 #include "base/range.hh"
44 #include "base/trace.hh"
45 #include "cpu/base_cpu.hh"
46 #include "cpu/exec_context.hh"
47 #include "cpu/exetrace.hh"
48 #include "cpu/full_cpu/smt.hh"
49 #include "cpu/simple_cpu/simple_cpu.hh"
50 #include "cpu/static_inst.hh"
51 #include "mem/base_mem.hh"
52 #include "mem/mem_interface.hh"
53 #include "sim/annotation.hh"
54 #include "sim/builder.hh"
55 #include "sim/debug.hh"
56 #include "sim/host.hh"
57 #include "sim/sim_events.hh"
58 #include "sim/sim_object.hh"
59 #include "sim/sim_stats.hh"
62 #include "base/remote_gdb.hh"
63 #include "dev/alpha_access.h"
64 #include "dev/pciareg.h"
65 #include "mem/functional_mem/memory_control.hh"
66 #include "mem/functional_mem/physical_memory.hh"
67 #include "sim/system.hh"
68 #include "targetarch/alpha_memory.hh"
69 #include "targetarch/vtophys.hh"
72 #include "mem/functional_mem/functional_memory.hh"
73 #include "sim/prog.hh"
78 SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU
*_cpu
)
79 : Event(&mainEventQueue
),
84 void SimpleCPU::CacheCompletionEvent::process()
86 cpu
->processCacheCompletion();
90 SimpleCPU::CacheCompletionEvent::description()
92 return "cache completion event";
96 SimpleCPU::SimpleCPU(const string
&_name
,
98 Counter max_insts_any_thread
,
99 Counter max_insts_all_threads
,
100 Counter max_loads_any_thread
,
101 Counter max_loads_all_threads
,
102 AlphaItb
*itb
, AlphaDtb
*dtb
,
103 FunctionalMemory
*mem
,
104 MemInterface
*icache_interface
,
105 MemInterface
*dcache_interface
,
107 : BaseCPU(_name
, /* number_of_threads */ 1,
108 max_insts_any_thread
, max_insts_all_threads
,
109 max_loads_any_thread
, max_loads_all_threads
,
112 SimpleCPU::SimpleCPU(const string
&_name
, Process
*_process
,
113 Counter max_insts_any_thread
,
114 Counter max_insts_all_threads
,
115 Counter max_loads_any_thread
,
116 Counter max_loads_all_threads
,
117 MemInterface
*icache_interface
,
118 MemInterface
*dcache_interface
)
119 : BaseCPU(_name
, /* number_of_threads */ 1,
120 max_insts_any_thread
, max_insts_all_threads
,
121 max_loads_any_thread
, max_loads_all_threads
),
123 tickEvent(this), xc(NULL
), cacheCompletionEvent(this)
127 xc
= new ExecContext(this, 0, system
, itb
, dtb
, mem
);
129 // initialize CPU, including PC
130 TheISA::initCPU(&xc
->regs
);
132 xc
= new ExecContext(this, /* thread_num */ 0, _process
, /* asid */ 0);
133 #endif // !FULL_SYSTEM
135 icacheInterface
= icache_interface
;
136 dcacheInterface
= dcache_interface
;
138 memReq
= new MemReq();
141 memReq
->data
= new uint8_t[64];
149 execContexts
.push_back(xc
);
152 SimpleCPU::~SimpleCPU()
158 SimpleCPU::switchOut()
160 _status
= SwitchedOut
;
161 if (tickEvent
.scheduled())
167 SimpleCPU::takeOverFrom(BaseCPU
*oldCPU
)
169 BaseCPU::takeOverFrom(oldCPU
);
171 assert(!tickEvent
.scheduled());
173 // if any of this CPU's ExecContexts are active, mark the CPU as
174 // running and schedule its tick event.
175 for (int i
= 0; i
< execContexts
.size(); ++i
) {
176 ExecContext
*xc
= execContexts
[i
];
177 if (xc
->status() == ExecContext::Active
&& _status
!= Running
) {
179 tickEvent
.schedule(curTick
);
188 SimpleCPU::execCtxStatusChg(int thread_num
) {
189 assert(thread_num
== 0);
192 if (xc
->status() == ExecContext::Active
)
200 SimpleCPU::regStats()
205 .name(name() + ".num_insts")
206 .desc("Number of instructions executed")
210 .name(name() + ".num_refs")
211 .desc("Number of memory references")
215 .name(name() + ".idle_cycles")
216 .desc("Number of idle cycles")
220 .name(name() + ".idle_fraction")
221 .desc("Percentage of idle cycles")
225 .name(name() + ".icache_stall_cycles")
226 .desc("ICache total stall cycles")
227 .prereq(icacheStallCycles
)
231 .name(name() + ".dcache_stall_cycles")
232 .desc("DCache total stall cycles")
233 .prereq(dcacheStallCycles
)
236 idleFraction
= idleCycles
/ simTicks
;
238 numInsts
= Statistics::scalar(numInst
);
239 simInsts
+= numInsts
;
243 SimpleCPU::serialize()
249 // do we need this anymore?? egh
250 childOut("itb", xc
->itb
);
251 childOut("dtb", xc
->dtb
);
252 childOut("physmem", physmem
);
256 for (int i
= 0; i
< NumIntRegs
; i
++) {
258 ccprintf(buf
, "R%02d", i
);
259 paramOut(buf
.str(), xc
->regs
.intRegFile
[i
]);
261 for (int i
= 0; i
< NumFloatRegs
; i
++) {
263 ccprintf(buf
, "F%02d", i
);
264 paramOut(buf
.str(), xc
->regs
.floatRegFile
.q
[i
]);
266 // CPUTraitsType::serializeSpecialRegs(getProxy(), xc->regs);
270 SimpleCPU::unserialize(IniFile
&db
, const string
&category
, ConfigNode
*node
)
274 for (int i
= 0; i
< NumIntRegs
; i
++) {
276 ccprintf(buf
, "R%02d", i
);
277 db
.findDefault(category
, buf
.str(), data
);
278 to_number(data
,xc
->regs
.intRegFile
[i
]);
280 for (int i
= 0; i
< NumFloatRegs
; i
++) {
282 ccprintf(buf
, "F%02d", i
);
283 db
.findDefault(category
, buf
.str(), data
);
284 to_number(data
.c_str(), xc
->regs
.floatRegFile
.q
[i
]);
287 // Read in Special registers
289 // CPUTraitsType::unserializeSpecialRegs(db,category,node,xc->regs);
293 change_thread_state(int thread_number
, int activate
, int priority
)
297 // precise architected memory state accessor macros
300 SimpleCPU::read(Addr addr
, T
& data
, unsigned flags
)
302 memReq
->reset(addr
, sizeof(T
), flags
);
304 // translate to physical address
305 Fault fault
= xc
->translateDataReadReq(memReq
);
307 // do functional access
308 if (fault
== No_Fault
)
309 fault
= xc
->read(memReq
, data
);
312 traceData
->setAddr(addr
);
313 if (fault
== No_Fault
)
314 traceData
->setData(data
);
317 // if we have a cache, do cache access too
318 if (fault
== No_Fault
&& dcacheInterface
) {
320 memReq
->completionEvent
= NULL
;
321 memReq
->time
= curTick
;
322 memReq
->flags
&= ~UNCACHEABLE
;
323 MemAccessResult result
= dcacheInterface
->access(memReq
);
325 // Ugly hack to get an event scheduled *only* if the access is
326 // a miss. We really should add first-class support for this
328 if (result
!= MA_HIT
&& dcacheInterface
->doEvents
) {
329 memReq
->completionEvent
= &cacheCompletionEvent
;
330 setStatus(DcacheMissStall
);
337 #ifndef DOXYGEN_SHOULD_SKIP_THIS
341 SimpleCPU::read(Addr addr
, uint64_t& data
, unsigned flags
);
345 SimpleCPU::read(Addr addr
, uint32_t& data
, unsigned flags
);
349 SimpleCPU::read(Addr addr
, uint16_t& data
, unsigned flags
);
353 SimpleCPU::read(Addr addr
, uint8_t& data
, unsigned flags
);
355 #endif //DOXYGEN_SHOULD_SKIP_THIS
359 SimpleCPU::read(Addr addr
, double& data
, unsigned flags
)
361 return read(addr
, *(uint64_t*)&data
, flags
);
366 SimpleCPU::read(Addr addr
, float& data
, unsigned flags
)
368 return read(addr
, *(uint32_t*)&data
, flags
);
374 SimpleCPU::read(Addr addr
, int32_t& data
, unsigned flags
)
376 return read(addr
, (uint32_t&)data
, flags
);
382 SimpleCPU::write(T data
, Addr addr
, unsigned flags
, uint64_t *res
)
385 traceData
->setAddr(addr
);
386 traceData
->setData(data
);
389 memReq
->reset(addr
, sizeof(T
), flags
);
391 // translate to physical address
392 Fault fault
= xc
->translateDataWriteReq(memReq
);
394 // do functional access
395 if (fault
== No_Fault
)
396 fault
= xc
->write(memReq
, data
);
398 if (fault
== No_Fault
&& dcacheInterface
) {
400 memcpy(memReq
->data
,(uint8_t *)&data
,memReq
->size
);
401 memReq
->completionEvent
= NULL
;
402 memReq
->time
= curTick
;
403 memReq
->flags
&= ~UNCACHEABLE
;
404 MemAccessResult result
= dcacheInterface
->access(memReq
);
406 // Ugly hack to get an event scheduled *only* if the access is
407 // a miss. We really should add first-class support for this
409 if (result
!= MA_HIT
&& dcacheInterface
->doEvents
) {
410 memReq
->completionEvent
= &cacheCompletionEvent
;
411 setStatus(DcacheMissStall
);
415 if (res
&& (fault
== No_Fault
))
416 *res
= memReq
->result
;
422 #ifndef DOXYGEN_SHOULD_SKIP_THIS
425 SimpleCPU::write(uint64_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
429 SimpleCPU::write(uint32_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
433 SimpleCPU::write(uint16_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
437 SimpleCPU::write(uint8_t data
, Addr addr
, unsigned flags
, uint64_t *res
);
439 #endif //DOXYGEN_SHOULD_SKIP_THIS
443 SimpleCPU::write(double data
, Addr addr
, unsigned flags
, uint64_t *res
)
445 return write(*(uint64_t*)&data
, addr
, flags
, res
);
450 SimpleCPU::write(float data
, Addr addr
, unsigned flags
, uint64_t *res
)
452 return write(*(uint32_t*)&data
, addr
, flags
, res
);
458 SimpleCPU::write(int32_t data
, Addr addr
, unsigned flags
, uint64_t *res
)
460 return write((uint32_t)data
, addr
, flags
, res
);
466 SimpleCPU::dbg_vtophys(Addr addr
)
468 return vtophys(xc
, addr
);
470 #endif // FULL_SYSTEM
476 SimpleCPU::processCacheCompletion()
479 case IcacheMissStall
:
480 icacheStallCycles
+= curTick
- lastIcacheStall
;
481 setStatus(IcacheMissComplete
);
483 case DcacheMissStall
:
484 dcacheStallCycles
+= curTick
- lastDcacheStall
;
488 // If this CPU has been switched out due to sampling/warm-up,
489 // ignore any further status changes (e.g., due to cache
490 // misses outstanding at the time of the switch).
493 panic("SimpleCPU::processCacheCompletion: bad state");
500 SimpleCPU::post_interrupt(int int_num
, int index
)
502 BaseCPU::post_interrupt(int_num
, index
);
504 if (xc
->status() == ExecContext::Suspended
) {
505 DPRINTF(IPI
,"Suspended Processor awoke\n");
506 xc
->setStatus(ExecContext::Active
);
507 Annotate::Resume(xc
);
510 #endif // FULL_SYSTEM
512 /* start simulation, program loaded, processor precise state initialized */
518 Fault fault
= No_Fault
;
521 if (AlphaISA::check_interrupts
&&
522 xc
->cpu
->check_interrupts() &&
523 !PC_PAL(xc
->regs
.pc
) &&
524 status() != IcacheMissComplete
) {
527 AlphaISA::check_interrupts
= 0;
528 IntReg
*ipr
= xc
->regs
.ipr
;
530 if (xc
->regs
.ipr
[TheISA::IPR_SIRR
]) {
531 for (int i
= TheISA::INTLEVEL_SOFTWARE_MIN
;
532 i
< TheISA::INTLEVEL_SOFTWARE_MAX
; i
++) {
533 if (ipr
[TheISA::IPR_SIRR
] & (ULL(1) << i
)) {
534 // See table 4-19 of 21164 hardware reference
535 ipl
= (i
- TheISA::INTLEVEL_SOFTWARE_MIN
) + 1;
536 summary
|= (ULL(1) << i
);
541 uint64_t interrupts
= xc
->cpu
->intr_status();
542 for (int i
= TheISA::INTLEVEL_EXTERNAL_MIN
;
543 i
< TheISA::INTLEVEL_EXTERNAL_MAX
; i
++) {
544 if (interrupts
& (ULL(1) << i
)) {
545 // See table 4-19 of 21164 hardware reference
547 summary
|= (ULL(1) << i
);
551 if (ipr
[TheISA::IPR_ASTRR
])
552 panic("asynchronous traps not implemented\n");
554 if (ipl
&& ipl
> xc
->regs
.ipr
[TheISA::IPR_IPLR
]) {
555 ipr
[TheISA::IPR_ISR
] = summary
;
556 ipr
[TheISA::IPR_INTID
] = ipl
;
557 xc
->ev5_trap(Interrupt_Fault
);
559 DPRINTF(Flow
, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
560 ipr
[TheISA::IPR_IPLR
], ipl
, summary
);
565 // maintain $r0 semantics
566 xc
->regs
.intRegFile
[ZeroReg
] = 0;
568 xc
->regs
.floatRegFile
.d
[ZeroReg
] = 0.0;
569 #endif // TARGET_ALPHA
571 if (status() == IcacheMissComplete
) {
572 // We've already fetched an instruction and were stalled on an
573 // I-cache miss. No need to fetch it again.
578 // Try to fetch an instruction
580 // set up memory request for instruction fetch
582 #define IFETCH_FLAGS(pc) ((pc) & 1) ? PHYSICAL : 0
584 #define IFETCH_FLAGS(pc) 0
588 memReq
->reset(xc
->regs
.pc
& ~3, sizeof(uint32_t),
589 IFETCH_FLAGS(xc
->regs
.pc
));
591 fault
= xc
->translateInstReq(memReq
);
593 if (fault
== No_Fault
)
594 fault
= xc
->mem
->read(memReq
, inst
);
596 if (icacheInterface
&& fault
== No_Fault
) {
597 memReq
->completionEvent
= NULL
;
599 memReq
->time
= curTick
;
600 memReq
->flags
&= ~UNCACHEABLE
;
601 MemAccessResult result
= icacheInterface
->access(memReq
);
603 // Ugly hack to get an event scheduled *only* if the access is
604 // a miss. We really should add first-class support for this
606 if (result
!= MA_HIT
&& icacheInterface
->doEvents
) {
607 memReq
->completionEvent
= &cacheCompletionEvent
;
608 setStatus(IcacheMissStall
);
614 // If we've got a valid instruction (i.e., no fault on instruction
615 // fetch), then execute it.
616 if (fault
== No_Fault
) {
618 // keep an instruction count
621 // check for instruction-count-based events
622 comInsnEventQueue
[0]->serviceEvents(numInst
);
624 // decode the instruction
625 StaticInstPtr
<TheISA
> si(inst
);
627 traceData
= Trace::getInstRecord(curTick
, xc
, this, si
,
631 xc
->regs
.opcode
= (inst
>> 26) & 0x3f;
632 xc
->regs
.ra
= (inst
>> 21) & 0x1f;
633 #endif // FULL_SYSTEM
637 fault
= si
->execute(this, xc
, traceData
);
639 if (si
->isMemRef()) {
645 comLoadEventQueue
[0]->serviceEvents(numLoad
);
649 traceData
->finalize();
651 } // if (fault == No_Fault)
653 if (fault
!= No_Fault
) {
656 #else // !FULL_SYSTEM
657 fatal("fault (%d) detected @ PC 0x%08p", fault
, xc
->regs
.pc
);
658 #endif // FULL_SYSTEM
661 // go to the next instruction
662 xc
->regs
.pc
= xc
->regs
.npc
;
663 xc
->regs
.npc
+= sizeof(MachInst
);
670 system
->pcEventQueue
.service(xc
);
671 } while (oldpc
!= xc
->regs
.pc
);
674 assert(status() == Running
||
676 status() == DcacheMissStall
);
678 if (status() == Running
&& !tickEvent
.scheduled())
679 tickEvent
.schedule(curTick
+ 1);
683 ////////////////////////////////////////////////////////////////////////
685 // SimpleCPU Simulation Object
687 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU
)
689 Param
<Counter
> max_insts_any_thread
;
690 Param
<Counter
> max_insts_all_threads
;
691 Param
<Counter
> max_loads_any_thread
;
692 Param
<Counter
> max_loads_all_threads
;
695 SimObjectParam
<AlphaItb
*> itb
;
696 SimObjectParam
<AlphaDtb
*> dtb
;
697 SimObjectParam
<FunctionalMemory
*> mem
;
698 SimObjectParam
<System
*> system
;
701 SimObjectParam
<Process
*> workload
;
702 #endif // FULL_SYSTEM
704 SimObjectParam
<BaseMem
*> icache
;
705 SimObjectParam
<BaseMem
*> dcache
;
707 Param
<bool> defer_registration
;
709 END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU
)
711 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU
)
713 INIT_PARAM_DFLT(max_insts_any_thread
,
714 "terminate when any thread reaches this insn count",
716 INIT_PARAM_DFLT(max_insts_all_threads
,
717 "terminate when all threads have reached this insn count",
719 INIT_PARAM_DFLT(max_loads_any_thread
,
720 "terminate when any thread reaches this load count",
722 INIT_PARAM_DFLT(max_loads_all_threads
,
723 "terminate when all threads have reached this load count",
727 INIT_PARAM(itb
, "Instruction TLB"),
728 INIT_PARAM(dtb
, "Data TLB"),
729 INIT_PARAM(mem
, "memory"),
730 INIT_PARAM(system
, "system object"),
731 INIT_PARAM_DFLT(mult
, "system clock multiplier", 1),
733 INIT_PARAM(workload
, "processes to run"),
734 #endif // FULL_SYSTEM
736 INIT_PARAM_DFLT(icache
, "L1 instruction cache object", NULL
),
737 INIT_PARAM_DFLT(dcache
, "L1 data cache object", NULL
),
738 INIT_PARAM_DFLT(defer_registration
, "defer registration with system "
739 "(for sampling)", false)
741 END_INIT_SIM_OBJECT_PARAMS(SimpleCPU
)
744 CREATE_SIM_OBJECT(SimpleCPU
)
749 panic("processor clock multiplier must be 1\n");
751 cpu
= new SimpleCPU(getInstanceName(), system
,
752 max_insts_any_thread
, max_insts_all_threads
,
753 max_loads_any_thread
, max_loads_all_threads
,
755 (icache
) ? icache
->getInterface() : NULL
,
756 (dcache
) ? dcache
->getInterface() : NULL
,
757 ticksPerSecond
* mult
);
760 cpu
= new SimpleCPU(getInstanceName(), workload
,
761 max_insts_any_thread
, max_insts_all_threads
,
762 max_loads_any_thread
, max_loads_all_threads
,
763 (icache
) ? icache
->getInterface() : NULL
,
764 (dcache
) ? dcache
->getInterface() : NULL
);
766 #endif // FULL_SYSTEM
768 if (!defer_registration
) {
769 cpu
->registerExecContexts();
775 REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU
)