cpu/simple_cpu/simple_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cmath>
  30 #include <cstdio>
  31 #include <cstdlib>
  32 #include <iostream>
  33 #include <iomanip>
  34 #include <list>
  35 #include <sstream>
  36 #include <string>
  37
  38 #include "base/cprintf.hh"
  39 #include "base/inifile.hh"
  40 #include "base/loader/symtab.hh"
  41 #include "base/misc.hh"
  42 #include "base/pollevent.hh"
  43 #include "base/range.hh"
  44 #include "base/trace.hh"
  45 #include "cpu/base_cpu.hh"
  46 #include "cpu/exec_context.hh"
  47 #include "cpu/exetrace.hh"
  48 #include "cpu/full_cpu/smt.hh"
  49 #include "cpu/simple_cpu/simple_cpu.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "mem/base_mem.hh"
  52 #include "mem/mem_interface.hh"
  53 #include "sim/annotation.hh"
  54 #include "sim/builder.hh"
  55 #include "sim/debug.hh"
  56 #include "sim/host.hh"
  57 #include "sim/sim_events.hh"
  58 #include "sim/sim_object.hh"
  59 #include "sim/sim_stats.hh"
  60
  61 #ifdef FULL_SYSTEM
  62 #include "base/remote_gdb.hh"
  63 #include "dev/alpha_access.h"
  64 #include "dev/pciareg.h"
  65 #include "mem/functional_mem/memory_control.hh"
  66 #include "mem/functional_mem/physical_memory.hh"
  67 #include "sim/system.hh"
  68 #include "targetarch/alpha_memory.hh"
  69 #include "targetarch/vtophys.hh"
  70 #else // !FULL_SYSTEM
  71 #include "eio/eio.hh"
  72 #include "mem/functional_mem/functional_memory.hh"
  73 #endif // FULL_SYSTEM
  74
  75 using namespace std;
  76
  77 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
  78     : Event(&mainEventQueue, 100), cpu(c)
  79 {
  80 }
  81
  82 void
  83 SimpleCPU::TickEvent::process()
  84 {
  85     cpu->tick();
  86 }
  87
  88 const char *
  89 SimpleCPU::TickEvent::description()
  90 {
  91     return "SimpleCPU tick event";
  92 }
  93
  94
  95 SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
  96     : Event(&mainEventQueue),
  97       cpu(_cpu)
  98 {
  99 }
 100
 101 void SimpleCPU::CacheCompletionEvent::process()
 102 {
 103     cpu->processCacheCompletion();
 104 }
 105
 106 const char *
 107 SimpleCPU::CacheCompletionEvent::description()
 108 {
 109     return "SimpleCPU cache completion event";
 110 }
 111
 112 #ifdef FULL_SYSTEM
 113 SimpleCPU::SimpleCPU(const string &_name,
 114                      System *_system,
 115                      Counter max_insts_any_thread,
 116                      Counter max_insts_all_threads,
 117                      Counter max_loads_any_thread,
 118                      Counter max_loads_all_threads,
 119                      AlphaItb *itb, AlphaDtb *dtb,
 120                      FunctionalMemory *mem,
 121                      MemInterface *icache_interface,
 122                      MemInterface *dcache_interface,
 123                      Tick freq)
 124     : BaseCPU(_name, /* number_of_threads */ 1,
 125               max_insts_any_thread, max_insts_all_threads,
 126               max_loads_any_thread, max_loads_all_threads,
 127               _system, freq),
 128 #else
 129 SimpleCPU::SimpleCPU(const string &_name, Process *_process,
 130                      Counter max_insts_any_thread,
 131                      Counter max_insts_all_threads,
 132                      Counter max_loads_any_thread,
 133                      Counter max_loads_all_threads,
 134                      MemInterface *icache_interface,
 135                      MemInterface *dcache_interface)
 136     : BaseCPU(_name, /* number_of_threads */ 1,
 137               max_insts_any_thread, max_insts_all_threads,
 138               max_loads_any_thread, max_loads_all_threads),
 139 #endif
 140       tickEvent(this), xc(NULL), cacheCompletionEvent(this)
 141 {
 142     _status = Idle;
 143 #ifdef FULL_SYSTEM
 144     xc = new ExecContext(this, 0, system, itb, dtb, mem);
 145
 146     // initialize CPU, including PC
 147     TheISA::initCPU(&xc->regs);
 148 #else
 149     xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
 150 #endif // !FULL_SYSTEM
 151
 152     icacheInterface = icache_interface;
 153     dcacheInterface = dcache_interface;
 154
 155     memReq = new MemReq();
 156     memReq->xc = xc;
 157     memReq->asid = 0;
 158     memReq->data = new uint8_t[64];
 159
 160     numInst = 0;
 161     startNumInst = 0;
 162     numLoad = 0;
 163     startNumLoad = 0;
 164     lastIcacheStall = 0;
 165     lastDcacheStall = 0;
 166
 167     execContexts.push_back(xc);
 168 }
 169
 170 SimpleCPU::~SimpleCPU()
 171 {
 172 }
 173
 174 void
 175 SimpleCPU::switchOut()
 176 {
 177     _status = SwitchedOut;
 178     if (tickEvent.scheduled())
 179         tickEvent.squash();
 180 }
 181
 182
 183 void
 184 SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 185 {
 186     BaseCPU::takeOverFrom(oldCPU);
 187
 188     assert(!tickEvent.scheduled());
 189
 190     // if any of this CPU's ExecContexts are active, mark the CPU as
 191     // running and schedule its tick event.
 192     for (int i = 0; i < execContexts.size(); ++i) {
 193         ExecContext *xc = execContexts[i];
 194         if (xc->status() == ExecContext::Active && _status != Running) {
 195             _status = Running;
 196             // the CpuSwitchEvent has a low priority, so it's
 197             // scheduled *after* the current cycle's tick event.  Thus
 198             // the first tick event for the new context should take
 199             // place on the *next* cycle.
 200             tickEvent.schedule(curTick+1);
 201         }
 202     }
 203
 204     oldCPU->switchOut();
 205 }
 206
 207
 208 void
 209 SimpleCPU::execCtxStatusChg(int thread_num) {
 210     assert(thread_num == 0);
 211     assert(xc);
 212
 213     if (xc->status() == ExecContext::Active)
 214         setStatus(Running);
 215     else
 216         setStatus(Idle);
 217 }
 218
 219
 220 void
 221 SimpleCPU::regStats()
 222 {
 223     using namespace Statistics;
 224
 225     BaseCPU::regStats();
 226
 227     numInsts
 228         .name(name() + ".num_insts")
 229         .desc("Number of instructions executed")
 230         ;
 231
 232     numMemRefs
 233         .name(name() + ".num_refs")
 234         .desc("Number of memory references")
 235         ;
 236
 237     idleFraction
 238         .name(name() + ".idle_fraction")
 239         .desc("Percentage of idle cycles")
 240         ;
 241
 242     icacheStallCycles
 243         .name(name() + ".icache_stall_cycles")
 244         .desc("ICache total stall cycles")
 245         .prereq(icacheStallCycles)
 246         ;
 247
 248     dcacheStallCycles
 249         .name(name() + ".dcache_stall_cycles")
 250         .desc("DCache total stall cycles")
 251         .prereq(dcacheStallCycles)
 252         ;
 253
 254     numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
 255     simInsts += numInsts;
 256 }
 257
 258 void
 259 SimpleCPU::resetStats()
 260 {
 261     startNumInst = numInst;
 262 }
 263
 264 void
 265 SimpleCPU::serialize(ostream &os)
 266 {
 267     SERIALIZE_ENUM(_status);
 268     SERIALIZE_SCALAR(inst);
 269     nameOut(os, csprintf("%s.xc", name()));
 270     xc->serialize(os);
 271     nameOut(os, csprintf("%s.tickEvent", name()));
 272     tickEvent.serialize(os);
 273     nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
 274     cacheCompletionEvent.serialize(os);
 275 }
 276
 277 void
 278 SimpleCPU::unserialize(Checkpoint *cp, const string &section)
 279 {
 280     UNSERIALIZE_ENUM(_status);
 281     UNSERIALIZE_SCALAR(inst);
 282     xc->unserialize(cp, csprintf("%s.xc", section));
 283     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 284     cacheCompletionEvent
 285         .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
 286 }
 287
 288 void
 289 change_thread_state(int thread_number, int activate, int priority)
 290 {
 291 }
 292
 293 // precise architected memory state accessor macros
 294 template <class T>
 295 Fault
 296 SimpleCPU::read(Addr addr, T& data, unsigned flags)
 297 {
 298     memReq->reset(addr, sizeof(T), flags);
 299
 300     // translate to physical address
 301     Fault fault = xc->translateDataReadReq(memReq);
 302
 303     // do functional access
 304     if (fault == No_Fault)
 305         fault = xc->read(memReq, data);
 306
 307     if (traceData) {
 308         traceData->setAddr(addr);
 309         if (fault == No_Fault)
 310             traceData->setData(data);
 311     }
 312
 313     // if we have a cache, do cache access too
 314     if (fault == No_Fault && dcacheInterface) {
 315         memReq->cmd = Read;
 316         memReq->completionEvent = NULL;
 317         memReq->time = curTick;
 318         memReq->flags &= ~UNCACHEABLE;
 319         MemAccessResult result = dcacheInterface->access(memReq);
 320
 321         // Ugly hack to get an event scheduled *only* if the access is
 322         // a miss.  We really should add first-class support for this
 323         // at some point.
 324         if (result != MA_HIT && dcacheInterface->doEvents) {
 325             memReq->completionEvent = &cacheCompletionEvent;
 326             setStatus(DcacheMissStall);
 327         }
 328     }
 329
 330     return fault;
 331 }
 332
 333 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 334
 335 template
 336 Fault
 337 SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
 338
 339 template
 340 Fault
 341 SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
 342
 343 template
 344 Fault
 345 SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
 346
 347 template
 348 Fault
 349 SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
 350
 351 #endif //DOXYGEN_SHOULD_SKIP_THIS
 352
 353 template<>
 354 Fault
 355 SimpleCPU::read(Addr addr, double& data, unsigned flags)
 356 {
 357     return read(addr, *(uint64_t*)&data, flags);
 358 }
 359
 360 template<>
 361 Fault
 362 SimpleCPU::read(Addr addr, float& data, unsigned flags)
 363 {
 364     return read(addr, *(uint32_t*)&data, flags);
 365 }
 366
 367
 368 template<>
 369 Fault
 370 SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
 371 {
 372     return read(addr, (uint32_t&)data, flags);
 373 }
 374
 375
 376 template <class T>
 377 Fault
 378 SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 379 {
 380     if (traceData) {
 381         traceData->setAddr(addr);
 382         traceData->setData(data);
 383     }
 384
 385     memReq->reset(addr, sizeof(T), flags);
 386
 387     // translate to physical address
 388     Fault fault = xc->translateDataWriteReq(memReq);
 389
 390     // do functional access
 391     if (fault == No_Fault)
 392         fault = xc->write(memReq, data);
 393
 394     if (fault == No_Fault && dcacheInterface) {
 395         memReq->cmd = Write;
 396         memcpy(memReq->data,(uint8_t *)&data,memReq->size);
 397         memReq->completionEvent = NULL;
 398         memReq->time = curTick;
 399         memReq->flags &= ~UNCACHEABLE;
 400         MemAccessResult result = dcacheInterface->access(memReq);
 401
 402         // Ugly hack to get an event scheduled *only* if the access is
 403         // a miss.  We really should add first-class support for this
 404         // at some point.
 405         if (result != MA_HIT && dcacheInterface->doEvents) {
 406             memReq->completionEvent = &cacheCompletionEvent;
 407             setStatus(DcacheMissStall);
 408         }
 409     }
 410
 411     if (res && (fault == No_Fault))
 412         *res = memReq->result;
 413
 414     return fault;
 415 }
 416
 417
 418 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 419 template
 420 Fault
 421 SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
 422
 423 template
 424 Fault
 425 SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
 426
 427 template
 428 Fault
 429 SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
 430
 431 template
 432 Fault
 433 SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
 434
 435 #endif //DOXYGEN_SHOULD_SKIP_THIS
 436
 437 template<>
 438 Fault
 439 SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 440 {
 441     return write(*(uint64_t*)&data, addr, flags, res);
 442 }
 443
 444 template<>
 445 Fault
 446 SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 447 {
 448     return write(*(uint32_t*)&data, addr, flags, res);
 449 }
 450
 451
 452 template<>
 453 Fault
 454 SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 455 {
 456     return write((uint32_t)data, addr, flags, res);
 457 }
 458
 459
 460 #ifdef FULL_SYSTEM
 461 Addr
 462 SimpleCPU::dbg_vtophys(Addr addr)
 463 {
 464     return vtophys(xc, addr);
 465 }
 466 #endif // FULL_SYSTEM
 467
 468 Tick save_cycle = 0;
 469
 470
 471 void
 472 SimpleCPU::processCacheCompletion()
 473 {
 474     switch (status()) {
 475       case IcacheMissStall:
 476         icacheStallCycles += curTick - lastIcacheStall;
 477         setStatus(IcacheMissComplete);
 478         break;
 479       case DcacheMissStall:
 480         dcacheStallCycles += curTick - lastDcacheStall;
 481         setStatus(Running);
 482         break;
 483       case SwitchedOut:
 484         // If this CPU has been switched out due to sampling/warm-up,
 485         // ignore any further status changes (e.g., due to cache
 486         // misses outstanding at the time of the switch).
 487         return;
 488       default:
 489         panic("SimpleCPU::processCacheCompletion: bad state");
 490         break;
 491     }
 492 }
 493
 494 #ifdef FULL_SYSTEM
 495 void
 496 SimpleCPU::post_interrupt(int int_num, int index)
 497 {
 498     BaseCPU::post_interrupt(int_num, index);
 499
 500     if (xc->status() == ExecContext::Suspended) {
 501                 DPRINTF(IPI,"Suspended Processor awoke\n");
 502         xc->setStatus(ExecContext::Active);
 503         Annotate::Resume(xc);
 504     }
 505 }
 506 #endif // FULL_SYSTEM
 507
 508 /* start simulation, program loaded, processor precise state initialized */
 509 void
 510 SimpleCPU::tick()
 511 {
 512     traceData = NULL;
 513
 514     Fault fault = No_Fault;
 515
 516 #ifdef FULL_SYSTEM
 517     if (AlphaISA::check_interrupts &&
 518         xc->cpu->check_interrupts() &&
 519         !PC_PAL(xc->regs.pc) &&
 520         status() != IcacheMissComplete) {
 521         int ipl = 0;
 522         int summary = 0;
 523         AlphaISA::check_interrupts = 0;
 524         IntReg *ipr = xc->regs.ipr;
 525
 526         if (xc->regs.ipr[TheISA::IPR_SIRR]) {
 527             for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
 528                  i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
 529                 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
 530                     // See table 4-19 of 21164 hardware reference
 531                     ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
 532                     summary |= (ULL(1) << i);
 533                 }
 534             }
 535         }
 536
 537         uint64_t interrupts = xc->cpu->intr_status();
 538         for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
 539             i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
 540             if (interrupts & (ULL(1) << i)) {
 541                 // See table 4-19 of 21164 hardware reference
 542                 ipl = i;
 543                 summary |= (ULL(1) << i);
 544             }
 545         }
 546
 547         if (ipr[TheISA::IPR_ASTRR])
 548             panic("asynchronous traps not implemented\n");
 549
 550         if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
 551             ipr[TheISA::IPR_ISR] = summary;
 552             ipr[TheISA::IPR_INTID] = ipl;
 553             xc->ev5_trap(Interrupt_Fault);
 554
 555             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 556                     ipr[TheISA::IPR_IPLR], ipl, summary);
 557         }
 558     }
 559 #endif
 560
 561     // maintain $r0 semantics
 562     xc->regs.intRegFile[ZeroReg] = 0;
 563 #ifdef TARGET_ALPHA
 564     xc->regs.floatRegFile.d[ZeroReg] = 0.0;
 565 #endif // TARGET_ALPHA
 566
 567     if (status() == IcacheMissComplete) {
 568         // We've already fetched an instruction and were stalled on an
 569         // I-cache miss.  No need to fetch it again.
 570
 571         setStatus(Running);
 572     }
 573     else {
 574         // Try to fetch an instruction
 575
 576         // set up memory request for instruction fetch
 577 #ifdef FULL_SYSTEM
 578 #define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 579 #else
 580 #define IFETCH_FLAGS(pc)        0
 581 #endif
 582
 583         memReq->cmd = Read;
 584         memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
 585                      IFETCH_FLAGS(xc->regs.pc));
 586
 587         fault = xc->translateInstReq(memReq);
 588
 589         if (fault == No_Fault)
 590             fault = xc->mem->read(memReq, inst);
 591
 592         if (icacheInterface && fault == No_Fault) {
 593             memReq->completionEvent = NULL;
 594
 595             memReq->time = curTick;
 596             memReq->flags &= ~UNCACHEABLE;
 597             MemAccessResult result = icacheInterface->access(memReq);
 598
 599             // Ugly hack to get an event scheduled *only* if the access is
 600             // a miss.  We really should add first-class support for this
 601             // at some point.
 602             if (result != MA_HIT && icacheInterface->doEvents) {
 603                 memReq->completionEvent = &cacheCompletionEvent;
 604                 setStatus(IcacheMissStall);
 605                 return;
 606             }
 607         }
 608     }
 609
 610     // If we've got a valid instruction (i.e., no fault on instruction
 611     // fetch), then execute it.
 612     if (fault == No_Fault) {
 613
 614         // keep an instruction count
 615         numInst++;
 616
 617         // check for instruction-count-based events
 618         comInsnEventQueue[0]->serviceEvents(numInst);
 619
 620         // decode the instruction
 621         StaticInstPtr<TheISA> si(inst);
 622
 623         traceData = Trace::getInstRecord(curTick, xc, this, si,
 624                                          xc->regs.pc);
 625
 626 #ifdef FULL_SYSTEM
 627         xc->regs.opcode = (inst >> 26) & 0x3f;
 628         xc->regs.ra = (inst >> 21) & 0x1f;
 629 #endif // FULL_SYSTEM
 630
 631         xc->func_exe_insn++;
 632
 633         fault = si->execute(this, xc, traceData);
 634 #ifdef FS_MEASURE
 635         if (!(xc->misspeculating()) && (xc->system->bin)) {
 636             SWContext *ctx = xc->swCtx;
 637             if (ctx && !ctx->callStack.empty()) {
 638                 if (si->isCall()) {
 639                     ctx->calls++;
 640                 }
 641                 if (si->isReturn()) {
 642                      if (ctx->calls == 0) {
 643                         fnCall *top = ctx->callStack.top();
 644                         DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
 645                         delete top;
 646                         ctx->callStack.pop();
 647                         if (ctx->callStack.empty())
 648                             xc->system->nonPath->activate();
 649                         else
 650                             ctx->callStack.top()->myBin->activate();
 651
 652                         xc->system->dumpState(xc);
 653                     } else {
 654                         ctx->calls--;
 655                     }
 656                 }
 657             }
 658         }
 659 #endif
 660         if (si->isMemRef()) {
 661             numMemRefs++;
 662         }
 663
 664         if (si->isLoad()) {
 665             ++numLoad;
 666             comLoadEventQueue[0]->serviceEvents(numLoad);
 667         }
 668
 669         if (traceData)
 670             traceData->finalize();
 671
 672     }   // if (fault == No_Fault)
 673
 674     if (fault != No_Fault) {
 675 #ifdef FULL_SYSTEM
 676         xc->ev5_trap(fault);
 677 #else // !FULL_SYSTEM
 678         fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
 679 #endif // FULL_SYSTEM
 680     }
 681     else {
 682         // go to the next instruction
 683         xc->regs.pc = xc->regs.npc;
 684         xc->regs.npc += sizeof(MachInst);
 685     }
 686
 687 #ifdef FULL_SYSTEM
 688     Addr oldpc;
 689     do {
 690         oldpc = xc->regs.pc;
 691         system->pcEventQueue.service(xc);
 692     } while (oldpc != xc->regs.pc);
 693 #endif
 694
 695     assert(status() == Running ||
 696            status() == Idle ||
 697            status() == DcacheMissStall);
 698
 699     if (status() == Running && !tickEvent.scheduled())
 700         tickEvent.schedule(curTick + 1);
 701 }
 702
 703
 704 ////////////////////////////////////////////////////////////////////////
 705 //
 706 //  SimpleCPU Simulation Object
 707 //
 708 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 709
 710     Param<Counter> max_insts_any_thread;
 711     Param<Counter> max_insts_all_threads;
 712     Param<Counter> max_loads_any_thread;
 713     Param<Counter> max_loads_all_threads;
 714
 715 #ifdef FULL_SYSTEM
 716     SimObjectParam<AlphaItb *> itb;
 717     SimObjectParam<AlphaDtb *> dtb;
 718     SimObjectParam<FunctionalMemory *> mem;
 719     SimObjectParam<System *> system;
 720     Param<int> mult;
 721 #else
 722     SimObjectParam<Process *> workload;
 723 #endif // FULL_SYSTEM
 724
 725     SimObjectParam<BaseMem *> icache;
 726     SimObjectParam<BaseMem *> dcache;
 727
 728     Param<bool> defer_registration;
 729
 730 END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 731
 732 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 733
 734     INIT_PARAM_DFLT(max_insts_any_thread,
 735                     "terminate when any thread reaches this insn count",
 736                     0),
 737     INIT_PARAM_DFLT(max_insts_all_threads,
 738                     "terminate when all threads have reached this insn count",
 739                     0),
 740     INIT_PARAM_DFLT(max_loads_any_thread,
 741                     "terminate when any thread reaches this load count",
 742                     0),
 743     INIT_PARAM_DFLT(max_loads_all_threads,
 744                     "terminate when all threads have reached this load count",
 745                     0),
 746
 747 #ifdef FULL_SYSTEM
 748     INIT_PARAM(itb, "Instruction TLB"),
 749     INIT_PARAM(dtb, "Data TLB"),
 750     INIT_PARAM(mem, "memory"),
 751     INIT_PARAM(system, "system object"),
 752     INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
 753 #else
 754     INIT_PARAM(workload, "processes to run"),
 755 #endif // FULL_SYSTEM
 756
 757     INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
 758     INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
 759     INIT_PARAM_DFLT(defer_registration, "defer registration with system "
 760                     "(for sampling)", false)
 761
 762 END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 763
 764
 765 CREATE_SIM_OBJECT(SimpleCPU)
 766 {
 767     SimpleCPU *cpu;
 768 #ifdef FULL_SYSTEM
 769     if (mult != 1)
 770         panic("processor clock multiplier must be 1\n");
 771
 772     cpu = new SimpleCPU(getInstanceName(), system,
 773                         max_insts_any_thread, max_insts_all_threads,
 774                         max_loads_any_thread, max_loads_all_threads,
 775                         itb, dtb, mem,
 776                         (icache) ? icache->getInterface() : NULL,
 777                         (dcache) ? dcache->getInterface() : NULL,
 778                         ticksPerSecond * mult);
 779 #else
 780
 781     cpu = new SimpleCPU(getInstanceName(), workload,
 782                         max_insts_any_thread, max_insts_all_threads,
 783                         max_loads_any_thread, max_loads_all_threads,
 784                         (icache) ? icache->getInterface() : NULL,
 785                         (dcache) ? dcache->getInterface() : NULL);
 786
 787 #endif // FULL_SYSTEM
 788
 789     if (!defer_registration) {
 790         cpu->registerExecContexts();
 791     }
 792
 793     return cpu;
 794 }
 795
 796 REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
 797