cpu/simple_cpu/simple_cpu.cc

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #include <cmath>
  30 #include <cstdio>
  31 #include <cstdlib>
  32 #include <iostream>
  33 #include <iomanip>
  34 #include <list>
  35 #include <sstream>
  36 #include <string>
  37
  38 #include "base/cprintf.hh"
  39 #include "base/inifile.hh"
  40 #include "base/loader/symtab.hh"
  41 #include "base/misc.hh"
  42 #include "base/pollevent.hh"
  43 #include "base/range.hh"
  44 #include "base/trace.hh"
  45 #include "cpu/base_cpu.hh"
  46 #include "cpu/exec_context.hh"
  47 #include "cpu/exetrace.hh"
  48 #include "cpu/full_cpu/smt.hh"
  49 #include "cpu/simple_cpu/simple_cpu.hh"
  50 #include "cpu/static_inst.hh"
  51 #include "mem/base_mem.hh"
  52 #include "mem/mem_interface.hh"
  53 #include "sim/annotation.hh"
  54 #include "sim/builder.hh"
  55 #include "sim/debug.hh"
  56 #include "sim/host.hh"
  57 #include "sim/sim_events.hh"
  58 #include "sim/sim_object.hh"
  59 #include "sim/sim_stats.hh"
  60
  61 #ifdef FULL_SYSTEM
  62 #include "base/remote_gdb.hh"
  63 #include "dev/alpha_access.h"
  64 #include "dev/pciareg.h"
  65 #include "mem/functional_mem/memory_control.hh"
  66 #include "mem/functional_mem/physical_memory.hh"
  67 #include "sim/system.hh"
  68 #include "targetarch/alpha_memory.hh"
  69 #include "targetarch/vtophys.hh"
  70 #else // !FULL_SYSTEM
  71 #include "eio/eio.hh"
  72 #include "mem/functional_mem/functional_memory.hh"
  73 #endif // FULL_SYSTEM
  74
  75 using namespace std;
  76
  77 SimpleCPU::TickEvent::TickEvent(SimpleCPU *c)
  78     : Event(&mainEventQueue, 100), cpu(c)
  79 {
  80 }
  81
  82 void
  83 SimpleCPU::TickEvent::process()
  84 {
  85     cpu->tick();
  86 }
  87
  88 const char *
  89 SimpleCPU::TickEvent::description()
  90 {
  91     return "SimpleCPU tick event";
  92 }
  93
  94
  95 SimpleCPU::CacheCompletionEvent::CacheCompletionEvent(SimpleCPU *_cpu)
  96     : Event(&mainEventQueue),
  97       cpu(_cpu)
  98 {
  99 }
 100
 101 void SimpleCPU::CacheCompletionEvent::process()
 102 {
 103     cpu->processCacheCompletion();
 104 }
 105
 106 const char *
 107 SimpleCPU::CacheCompletionEvent::description()
 108 {
 109     return "SimpleCPU cache completion event";
 110 }
 111
 112 #ifdef FULL_SYSTEM
 113 SimpleCPU::SimpleCPU(const string &_name,
 114                      System *_system,
 115                      Counter max_insts_any_thread,
 116                      Counter max_insts_all_threads,
 117                      Counter max_loads_any_thread,
 118                      Counter max_loads_all_threads,
 119                      AlphaItb *itb, AlphaDtb *dtb,
 120                      FunctionalMemory *mem,
 121                      MemInterface *icache_interface,
 122                      MemInterface *dcache_interface,
 123                      Tick freq)
 124     : BaseCPU(_name, /* number_of_threads */ 1,
 125               max_insts_any_thread, max_insts_all_threads,
 126               max_loads_any_thread, max_loads_all_threads,
 127               _system, freq),
 128 #else
 129 SimpleCPU::SimpleCPU(const string &_name, Process *_process,
 130                      Counter max_insts_any_thread,
 131                      Counter max_insts_all_threads,
 132                      Counter max_loads_any_thread,
 133                      Counter max_loads_all_threads,
 134                      MemInterface *icache_interface,
 135                      MemInterface *dcache_interface)
 136     : BaseCPU(_name, /* number_of_threads */ 1,
 137               max_insts_any_thread, max_insts_all_threads,
 138               max_loads_any_thread, max_loads_all_threads),
 139 #endif
 140       tickEvent(this), xc(NULL), cacheCompletionEvent(this)
 141 {
 142     _status = Idle;
 143 #ifdef FULL_SYSTEM
 144     xc = new ExecContext(this, 0, system, itb, dtb, mem);
 145
 146     // initialize CPU, including PC
 147     TheISA::initCPU(&xc->regs);
 148 #else
 149     xc = new ExecContext(this, /* thread_num */ 0, _process, /* asid */ 0);
 150 #endif // !FULL_SYSTEM
 151
 152     icacheInterface = icache_interface;
 153     dcacheInterface = dcache_interface;
 154
 155     memReq = new MemReq();
 156     memReq->xc = xc;
 157     memReq->asid = 0;
 158     memReq->data = new uint8_t[64];
 159
 160     numInst = 0;
 161     startNumInst = 0;
 162     numLoad = 0;
 163     startNumLoad = 0;
 164     lastIcacheStall = 0;
 165     lastDcacheStall = 0;
 166
 167     execContexts.push_back(xc);
 168 }
 169
 170 SimpleCPU::~SimpleCPU()
 171 {
 172 }
 173
 174 void
 175 SimpleCPU::switchOut()
 176 {
 177     _status = SwitchedOut;
 178     if (tickEvent.scheduled())
 179         tickEvent.squash();
 180 }
 181
 182
 183 void
 184 SimpleCPU::takeOverFrom(BaseCPU *oldCPU)
 185 {
 186     BaseCPU::takeOverFrom(oldCPU);
 187
 188     assert(!tickEvent.scheduled());
 189
 190     // if any of this CPU's ExecContexts are active, mark the CPU as
 191     // running and schedule its tick event.
 192     for (int i = 0; i < execContexts.size(); ++i) {
 193         ExecContext *xc = execContexts[i];
 194         if (xc->status() == ExecContext::Active && _status != Running) {
 195             _status = Running;
 196             // the CpuSwitchEvent has a low priority, so it's
 197             // scheduled *after* the current cycle's tick event.  Thus
 198             // the first tick event for the new context should take
 199             // place on the *next* cycle.
 200             tickEvent.schedule(curTick+1);
 201         }
 202     }
 203
 204     oldCPU->switchOut();
 205 }
 206
 207
 208 void
 209 SimpleCPU::execCtxStatusChg(int thread_num) {
 210     assert(thread_num == 0);
 211     assert(xc);
 212
 213     if (xc->status() == ExecContext::Active)
 214         setStatus(Running);
 215     else
 216         setStatus(Idle);
 217 }
 218
 219 void
 220 SimpleCPU::setStatus(Status new_status)
 221 {
 222     Status old_status = status();
 223
 224     // We should never even get here if the CPU has been switched out.
 225     assert(old_status != SwitchedOut);
 226
 227     _status = new_status;
 228
 229     switch (status()) {
 230       case IcacheMissStall:
 231         assert(old_status == Running);
 232         lastIcacheStall = curTick;
 233         if (tickEvent.scheduled())
 234             tickEvent.squash();
 235         break;
 236
 237       case IcacheMissComplete:
 238         assert(old_status == IcacheMissStall);
 239         if (tickEvent.squashed())
 240             tickEvent.reschedule(curTick + 1);
 241         else if (!tickEvent.scheduled())
 242             tickEvent.schedule(curTick + 1);
 243         break;
 244
 245       case DcacheMissStall:
 246         assert(old_status == Running);
 247         lastDcacheStall = curTick;
 248         if (tickEvent.scheduled())
 249             tickEvent.squash();
 250         break;
 251
 252       case Idle:
 253         assert(old_status == Running);
 254         notIdleFraction--;
 255         if (tickEvent.scheduled())
 256             tickEvent.squash();
 257         break;
 258
 259       case Running:
 260         assert(old_status == Idle ||
 261                old_status == DcacheMissStall ||
 262                old_status == IcacheMissComplete);
 263         if (old_status == Idle)
 264             notIdleFraction++;
 265
 266         if (tickEvent.squashed())
 267             tickEvent.reschedule(curTick + 1);
 268         else if (!tickEvent.scheduled())
 269             tickEvent.schedule(curTick + 1);
 270         break;
 271
 272       default:
 273         panic("can't get here");
 274     }
 275 }
 276
 277 void
 278 SimpleCPU::regStats()
 279 {
 280     using namespace Statistics;
 281
 282     BaseCPU::regStats();
 283
 284     numInsts
 285         .name(name() + ".num_insts")
 286         .desc("Number of instructions executed")
 287         ;
 288
 289     numMemRefs
 290         .name(name() + ".num_refs")
 291         .desc("Number of memory references")
 292         ;
 293
 294     idleFraction
 295         .name(name() + ".idle_fraction")
 296         .desc("Percentage of idle cycles")
 297         ;
 298
 299     icacheStallCycles
 300         .name(name() + ".icache_stall_cycles")
 301         .desc("ICache total stall cycles")
 302         .prereq(icacheStallCycles)
 303         ;
 304
 305     dcacheStallCycles
 306         .name(name() + ".dcache_stall_cycles")
 307         .desc("DCache total stall cycles")
 308         .prereq(dcacheStallCycles)
 309         ;
 310
 311     idleFraction = constant(1.0) - notIdleFraction;
 312     numInsts = Statistics::scalar(numInst) - Statistics::scalar(startNumInst);
 313     simInsts += numInsts;
 314 }
 315
 316 void
 317 SimpleCPU::resetStats()
 318 {
 319     startNumInst = numInst;
 320     notIdleFraction = (_status != Idle);
 321 }
 322
 323 void
 324 SimpleCPU::serialize(ostream &os)
 325 {
 326     SERIALIZE_ENUM(_status);
 327     SERIALIZE_SCALAR(inst);
 328     nameOut(os, csprintf("%s.xc", name()));
 329     xc->serialize(os);
 330     nameOut(os, csprintf("%s.tickEvent", name()));
 331     tickEvent.serialize(os);
 332     nameOut(os, csprintf("%s.cacheCompletionEvent", name()));
 333     cacheCompletionEvent.serialize(os);
 334 }
 335
 336 void
 337 SimpleCPU::unserialize(Checkpoint *cp, const string &section)
 338 {
 339     UNSERIALIZE_ENUM(_status);
 340     UNSERIALIZE_SCALAR(inst);
 341     xc->unserialize(cp, csprintf("%s.xc", section));
 342     tickEvent.unserialize(cp, csprintf("%s.tickEvent", section));
 343     cacheCompletionEvent
 344         .unserialize(cp, csprintf("%s.cacheCompletionEvent", section));
 345 }
 346
 347 void
 348 change_thread_state(int thread_number, int activate, int priority)
 349 {
 350 }
 351
 352 // precise architected memory state accessor macros
 353 template <class T>
 354 Fault
 355 SimpleCPU::read(Addr addr, T& data, unsigned flags)
 356 {
 357     memReq->reset(addr, sizeof(T), flags);
 358
 359     // translate to physical address
 360     Fault fault = xc->translateDataReadReq(memReq);
 361
 362     // do functional access
 363     if (fault == No_Fault)
 364         fault = xc->read(memReq, data);
 365
 366     if (traceData) {
 367         traceData->setAddr(addr);
 368         if (fault == No_Fault)
 369             traceData->setData(data);
 370     }
 371
 372     // if we have a cache, do cache access too
 373     if (fault == No_Fault && dcacheInterface) {
 374         memReq->cmd = Read;
 375         memReq->completionEvent = NULL;
 376         memReq->time = curTick;
 377         memReq->flags &= ~UNCACHEABLE;
 378         MemAccessResult result = dcacheInterface->access(memReq);
 379
 380         // Ugly hack to get an event scheduled *only* if the access is
 381         // a miss.  We really should add first-class support for this
 382         // at some point.
 383         if (result != MA_HIT && dcacheInterface->doEvents) {
 384             memReq->completionEvent = &cacheCompletionEvent;
 385             setStatus(DcacheMissStall);
 386         }
 387     }
 388
 389     return fault;
 390 }
 391
 392 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 393
 394 template
 395 Fault
 396 SimpleCPU::read(Addr addr, uint64_t& data, unsigned flags);
 397
 398 template
 399 Fault
 400 SimpleCPU::read(Addr addr, uint32_t& data, unsigned flags);
 401
 402 template
 403 Fault
 404 SimpleCPU::read(Addr addr, uint16_t& data, unsigned flags);
 405
 406 template
 407 Fault
 408 SimpleCPU::read(Addr addr, uint8_t& data, unsigned flags);
 409
 410 #endif //DOXYGEN_SHOULD_SKIP_THIS
 411
 412 template<>
 413 Fault
 414 SimpleCPU::read(Addr addr, double& data, unsigned flags)
 415 {
 416     return read(addr, *(uint64_t*)&data, flags);
 417 }
 418
 419 template<>
 420 Fault
 421 SimpleCPU::read(Addr addr, float& data, unsigned flags)
 422 {
 423     return read(addr, *(uint32_t*)&data, flags);
 424 }
 425
 426
 427 template<>
 428 Fault
 429 SimpleCPU::read(Addr addr, int32_t& data, unsigned flags)
 430 {
 431     return read(addr, (uint32_t&)data, flags);
 432 }
 433
 434
 435 template <class T>
 436 Fault
 437 SimpleCPU::write(T data, Addr addr, unsigned flags, uint64_t *res)
 438 {
 439     if (traceData) {
 440         traceData->setAddr(addr);
 441         traceData->setData(data);
 442     }
 443
 444     memReq->reset(addr, sizeof(T), flags);
 445
 446     // translate to physical address
 447     Fault fault = xc->translateDataWriteReq(memReq);
 448
 449     // do functional access
 450     if (fault == No_Fault)
 451         fault = xc->write(memReq, data);
 452
 453     if (fault == No_Fault && dcacheInterface) {
 454         memReq->cmd = Write;
 455         memcpy(memReq->data,(uint8_t *)&data,memReq->size);
 456         memReq->completionEvent = NULL;
 457         memReq->time = curTick;
 458         memReq->flags &= ~UNCACHEABLE;
 459         MemAccessResult result = dcacheInterface->access(memReq);
 460
 461         // Ugly hack to get an event scheduled *only* if the access is
 462         // a miss.  We really should add first-class support for this
 463         // at some point.
 464         if (result != MA_HIT && dcacheInterface->doEvents) {
 465             memReq->completionEvent = &cacheCompletionEvent;
 466             setStatus(DcacheMissStall);
 467         }
 468     }
 469
 470     if (res && (fault == No_Fault))
 471         *res = memReq->result;
 472
 473     return fault;
 474 }
 475
 476
 477 #ifndef DOXYGEN_SHOULD_SKIP_THIS
 478 template
 479 Fault
 480 SimpleCPU::write(uint64_t data, Addr addr, unsigned flags, uint64_t *res);
 481
 482 template
 483 Fault
 484 SimpleCPU::write(uint32_t data, Addr addr, unsigned flags, uint64_t *res);
 485
 486 template
 487 Fault
 488 SimpleCPU::write(uint16_t data, Addr addr, unsigned flags, uint64_t *res);
 489
 490 template
 491 Fault
 492 SimpleCPU::write(uint8_t data, Addr addr, unsigned flags, uint64_t *res);
 493
 494 #endif //DOXYGEN_SHOULD_SKIP_THIS
 495
 496 template<>
 497 Fault
 498 SimpleCPU::write(double data, Addr addr, unsigned flags, uint64_t *res)
 499 {
 500     return write(*(uint64_t*)&data, addr, flags, res);
 501 }
 502
 503 template<>
 504 Fault
 505 SimpleCPU::write(float data, Addr addr, unsigned flags, uint64_t *res)
 506 {
 507     return write(*(uint32_t*)&data, addr, flags, res);
 508 }
 509
 510
 511 template<>
 512 Fault
 513 SimpleCPU::write(int32_t data, Addr addr, unsigned flags, uint64_t *res)
 514 {
 515     return write((uint32_t)data, addr, flags, res);
 516 }
 517
 518
 519 #ifdef FULL_SYSTEM
 520 Addr
 521 SimpleCPU::dbg_vtophys(Addr addr)
 522 {
 523     return vtophys(xc, addr);
 524 }
 525 #endif // FULL_SYSTEM
 526
 527 Tick save_cycle = 0;
 528
 529
 530 void
 531 SimpleCPU::processCacheCompletion()
 532 {
 533     switch (status()) {
 534       case IcacheMissStall:
 535         icacheStallCycles += curTick - lastIcacheStall;
 536         setStatus(IcacheMissComplete);
 537         break;
 538       case DcacheMissStall:
 539         dcacheStallCycles += curTick - lastDcacheStall;
 540         setStatus(Running);
 541         break;
 542       case SwitchedOut:
 543         // If this CPU has been switched out due to sampling/warm-up,
 544         // ignore any further status changes (e.g., due to cache
 545         // misses outstanding at the time of the switch).
 546         return;
 547       default:
 548         panic("SimpleCPU::processCacheCompletion: bad state");
 549         break;
 550     }
 551 }
 552
 553 #ifdef FULL_SYSTEM
 554 void
 555 SimpleCPU::post_interrupt(int int_num, int index)
 556 {
 557     BaseCPU::post_interrupt(int_num, index);
 558
 559     if (xc->status() == ExecContext::Suspended) {
 560                 DPRINTF(IPI,"Suspended Processor awoke\n");
 561         xc->setStatus(ExecContext::Active);
 562         Annotate::Resume(xc);
 563     }
 564 }
 565 #endif // FULL_SYSTEM
 566
 567 /* start simulation, program loaded, processor precise state initialized */
 568 void
 569 SimpleCPU::tick()
 570 {
 571     traceData = NULL;
 572
 573     Fault fault = No_Fault;
 574
 575 #ifdef FULL_SYSTEM
 576     if (AlphaISA::check_interrupts &&
 577         xc->cpu->check_interrupts() &&
 578         !PC_PAL(xc->regs.pc) &&
 579         status() != IcacheMissComplete) {
 580         int ipl = 0;
 581         int summary = 0;
 582         AlphaISA::check_interrupts = 0;
 583         IntReg *ipr = xc->regs.ipr;
 584
 585         if (xc->regs.ipr[TheISA::IPR_SIRR]) {
 586             for (int i = TheISA::INTLEVEL_SOFTWARE_MIN;
 587                  i < TheISA::INTLEVEL_SOFTWARE_MAX; i++) {
 588                 if (ipr[TheISA::IPR_SIRR] & (ULL(1) << i)) {
 589                     // See table 4-19 of 21164 hardware reference
 590                     ipl = (i - TheISA::INTLEVEL_SOFTWARE_MIN) + 1;
 591                     summary |= (ULL(1) << i);
 592                 }
 593             }
 594         }
 595
 596         uint64_t interrupts = xc->cpu->intr_status();
 597         for (int i = TheISA::INTLEVEL_EXTERNAL_MIN;
 598             i < TheISA::INTLEVEL_EXTERNAL_MAX; i++) {
 599             if (interrupts & (ULL(1) << i)) {
 600                 // See table 4-19 of 21164 hardware reference
 601                 ipl = i;
 602                 summary |= (ULL(1) << i);
 603             }
 604         }
 605
 606         if (ipr[TheISA::IPR_ASTRR])
 607             panic("asynchronous traps not implemented\n");
 608
 609         if (ipl && ipl > xc->regs.ipr[TheISA::IPR_IPLR]) {
 610             ipr[TheISA::IPR_ISR] = summary;
 611             ipr[TheISA::IPR_INTID] = ipl;
 612             xc->ev5_trap(Interrupt_Fault);
 613
 614             DPRINTF(Flow, "Interrupt! IPLR=%d ipl=%d summary=%x\n",
 615                     ipr[TheISA::IPR_IPLR], ipl, summary);
 616         }
 617     }
 618 #endif
 619
 620     // maintain $r0 semantics
 621     xc->regs.intRegFile[ZeroReg] = 0;
 622 #ifdef TARGET_ALPHA
 623     xc->regs.floatRegFile.d[ZeroReg] = 0.0;
 624 #endif // TARGET_ALPHA
 625
 626     if (status() == IcacheMissComplete) {
 627         // We've already fetched an instruction and were stalled on an
 628         // I-cache miss.  No need to fetch it again.
 629
 630         setStatus(Running);
 631     }
 632     else {
 633         // Try to fetch an instruction
 634
 635         // set up memory request for instruction fetch
 636 #ifdef FULL_SYSTEM
 637 #define IFETCH_FLAGS(pc)        ((pc) & 1) ? PHYSICAL : 0
 638 #else
 639 #define IFETCH_FLAGS(pc)        0
 640 #endif
 641
 642         memReq->cmd = Read;
 643         memReq->reset(xc->regs.pc & ~3, sizeof(uint32_t),
 644                      IFETCH_FLAGS(xc->regs.pc));
 645
 646         fault = xc->translateInstReq(memReq);
 647
 648         if (fault == No_Fault)
 649             fault = xc->mem->read(memReq, inst);
 650
 651         if (icacheInterface && fault == No_Fault) {
 652             memReq->completionEvent = NULL;
 653
 654             memReq->time = curTick;
 655             memReq->flags &= ~UNCACHEABLE;
 656             MemAccessResult result = icacheInterface->access(memReq);
 657
 658             // Ugly hack to get an event scheduled *only* if the access is
 659             // a miss.  We really should add first-class support for this
 660             // at some point.
 661             if (result != MA_HIT && icacheInterface->doEvents) {
 662                 memReq->completionEvent = &cacheCompletionEvent;
 663                 setStatus(IcacheMissStall);
 664                 return;
 665             }
 666         }
 667     }
 668
 669     // If we've got a valid instruction (i.e., no fault on instruction
 670     // fetch), then execute it.
 671     if (fault == No_Fault) {
 672
 673         // keep an instruction count
 674         numInst++;
 675
 676         // check for instruction-count-based events
 677         comInsnEventQueue[0]->serviceEvents(numInst);
 678
 679         // decode the instruction
 680         StaticInstPtr<TheISA> si(inst);
 681
 682         traceData = Trace::getInstRecord(curTick, xc, this, si,
 683                                          xc->regs.pc);
 684
 685 #ifdef FULL_SYSTEM
 686         xc->regs.opcode = (inst >> 26) & 0x3f;
 687         xc->regs.ra = (inst >> 21) & 0x1f;
 688 #endif // FULL_SYSTEM
 689
 690         xc->func_exe_insn++;
 691
 692         fault = si->execute(this, xc, traceData);
 693 #ifdef FS_MEASURE
 694         if (!(xc->misspeculating()) && (xc->system->bin)) {
 695             SWContext *ctx = xc->swCtx;
 696             if (ctx && !ctx->callStack.empty()) {
 697                 if (si->isCall()) {
 698                     ctx->calls++;
 699                 }
 700                 if (si->isReturn()) {
 701                      if (ctx->calls == 0) {
 702                         fnCall *top = ctx->callStack.top();
 703                         DPRINTF(TCPIP, "Removing %s from callstack.\n", top->name);
 704                         delete top;
 705                         ctx->callStack.pop();
 706                         if (ctx->callStack.empty())
 707                             xc->system->nonPath->activate();
 708                         else
 709                             ctx->callStack.top()->myBin->activate();
 710
 711                         xc->system->dumpState(xc);
 712                     } else {
 713                         ctx->calls--;
 714                     }
 715                 }
 716             }
 717         }
 718 #endif
 719         if (si->isMemRef()) {
 720             numMemRefs++;
 721         }
 722
 723         if (si->isLoad()) {
 724             ++numLoad;
 725             comLoadEventQueue[0]->serviceEvents(numLoad);
 726         }
 727
 728         if (traceData)
 729             traceData->finalize();
 730
 731     }   // if (fault == No_Fault)
 732
 733     if (fault != No_Fault) {
 734 #ifdef FULL_SYSTEM
 735         xc->ev5_trap(fault);
 736 #else // !FULL_SYSTEM
 737         fatal("fault (%d) detected @ PC 0x%08p", fault, xc->regs.pc);
 738 #endif // FULL_SYSTEM
 739     }
 740     else {
 741         // go to the next instruction
 742         xc->regs.pc = xc->regs.npc;
 743         xc->regs.npc += sizeof(MachInst);
 744     }
 745
 746 #ifdef FULL_SYSTEM
 747     Addr oldpc;
 748     do {
 749         oldpc = xc->regs.pc;
 750         system->pcEventQueue.service(xc);
 751     } while (oldpc != xc->regs.pc);
 752 #endif
 753
 754     assert(status() == Running ||
 755            status() == Idle ||
 756            status() == DcacheMissStall);
 757
 758     if (status() == Running && !tickEvent.scheduled())
 759         tickEvent.schedule(curTick + 1);
 760 }
 761
 762
 763 ////////////////////////////////////////////////////////////////////////
 764 //
 765 //  SimpleCPU Simulation Object
 766 //
 767 BEGIN_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 768
 769     Param<Counter> max_insts_any_thread;
 770     Param<Counter> max_insts_all_threads;
 771     Param<Counter> max_loads_any_thread;
 772     Param<Counter> max_loads_all_threads;
 773
 774 #ifdef FULL_SYSTEM
 775     SimObjectParam<AlphaItb *> itb;
 776     SimObjectParam<AlphaDtb *> dtb;
 777     SimObjectParam<FunctionalMemory *> mem;
 778     SimObjectParam<System *> system;
 779     Param<int> mult;
 780 #else
 781     SimObjectParam<Process *> workload;
 782 #endif // FULL_SYSTEM
 783
 784     SimObjectParam<BaseMem *> icache;
 785     SimObjectParam<BaseMem *> dcache;
 786
 787     Param<bool> defer_registration;
 788
 789 END_DECLARE_SIM_OBJECT_PARAMS(SimpleCPU)
 790
 791 BEGIN_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 792
 793     INIT_PARAM_DFLT(max_insts_any_thread,
 794                     "terminate when any thread reaches this insn count",
 795                     0),
 796     INIT_PARAM_DFLT(max_insts_all_threads,
 797                     "terminate when all threads have reached this insn count",
 798                     0),
 799     INIT_PARAM_DFLT(max_loads_any_thread,
 800                     "terminate when any thread reaches this load count",
 801                     0),
 802     INIT_PARAM_DFLT(max_loads_all_threads,
 803                     "terminate when all threads have reached this load count",
 804                     0),
 805
 806 #ifdef FULL_SYSTEM
 807     INIT_PARAM(itb, "Instruction TLB"),
 808     INIT_PARAM(dtb, "Data TLB"),
 809     INIT_PARAM(mem, "memory"),
 810     INIT_PARAM(system, "system object"),
 811     INIT_PARAM_DFLT(mult, "system clock multiplier", 1),
 812 #else
 813     INIT_PARAM(workload, "processes to run"),
 814 #endif // FULL_SYSTEM
 815
 816     INIT_PARAM_DFLT(icache, "L1 instruction cache object", NULL),
 817     INIT_PARAM_DFLT(dcache, "L1 data cache object", NULL),
 818     INIT_PARAM_DFLT(defer_registration, "defer registration with system "
 819                     "(for sampling)", false)
 820
 821 END_INIT_SIM_OBJECT_PARAMS(SimpleCPU)
 822
 823
 824 CREATE_SIM_OBJECT(SimpleCPU)
 825 {
 826     SimpleCPU *cpu;
 827 #ifdef FULL_SYSTEM
 828     if (mult != 1)
 829         panic("processor clock multiplier must be 1\n");
 830
 831     cpu = new SimpleCPU(getInstanceName(), system,
 832                         max_insts_any_thread, max_insts_all_threads,
 833                         max_loads_any_thread, max_loads_all_threads,
 834                         itb, dtb, mem,
 835                         (icache) ? icache->getInterface() : NULL,
 836                         (dcache) ? dcache->getInterface() : NULL,
 837                         ticksPerSecond * mult);
 838 #else
 839
 840     cpu = new SimpleCPU(getInstanceName(), workload,
 841                         max_insts_any_thread, max_insts_all_threads,
 842                         max_loads_any_thread, max_loads_all_threads,
 843                         (icache) ? icache->getInterface() : NULL,
 844                         (dcache) ? dcache->getInterface() : NULL);
 845
 846 #endif // FULL_SYSTEM
 847
 848     if (!defer_registration) {
 849         cpu->registerExecContexts();
 850     }
 851
 852     return cpu;
 853 }
 854
 855 REGISTER_SIM_OBJECT("SimpleCPU", SimpleCPU)
 856