2 * Copyright (c) 2003 The Regents of The University of Michigan
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29 #ifndef __SIMPLE_CPU_HH__
30 #define __SIMPLE_CPU_HH__
32 #include "cpu/base_cpu.hh"
33 #include "sim/eventq.hh"
34 #include "base/loader/symtab.hh"
35 #include "cpu/pc_event.hh"
36 #include "base/statistics.hh"
39 // forward declarations
58 class SimpleCPU : public BaseCPU
61 // main simulation loop (one cycle)
65 class TickEvent : public Event
71 TickEvent(SimpleCPU *c);
73 const char *description();
78 /// Schedule tick event, regardless of its current state.
79 void scheduleTickEvent(int delay)
81 if (tickEvent.squashed())
82 tickEvent.reschedule(curTick + delay);
83 else if (!tickEvent.scheduled())
84 tickEvent.schedule(curTick + delay);
87 /// Unschedule tick event, regardless of its current state.
88 void unscheduleTickEvent()
90 if (tickEvent.scheduled())
95 Trace::InstRecord *traceData;
97 void trace_data(T data) {
99 traceData->setData(data);
118 void post_interrupt(int int_num, int index);
120 void zero_fill_64(Addr addr) {
121 static int warned = 0;
123 warn ("WH64 is not implemented");
130 SimpleCPU(const std::string &_name,
132 Counter max_insts_any_thread, Counter max_insts_all_threads,
133 Counter max_loads_any_thread, Counter max_loads_all_threads,
134 AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
135 MemInterface *icache_interface, MemInterface *dcache_interface,
136 bool _def_reg, Tick freq);
140 SimpleCPU(const std::string &_name, Process *_process,
141 Counter max_insts_any_thread,
142 Counter max_insts_all_threads,
143 Counter max_loads_any_thread,
144 Counter max_loads_all_threads,
145 MemInterface *icache_interface, MemInterface *dcache_interface,
150 virtual ~SimpleCPU();
157 void takeOverFrom(BaseCPU *oldCPU);
160 Addr dbg_vtophys(Addr addr);
165 // L1 instruction cache
166 MemInterface *icacheInterface;
169 MemInterface *dcacheInterface;
171 bool defer_registration;
173 // current instruction
176 // Refcounted pointer to the one memory request.
179 class CacheCompletionEvent : public Event
185 CacheCompletionEvent(SimpleCPU *_cpu);
187 virtual void process();
188 virtual const char *description();
191 CacheCompletionEvent cacheCompletionEvent;
193 Status status() const { return _status; }
195 virtual void activateContext(int thread_num, int delay);
196 virtual void suspendContext(int thread_num);
197 virtual void deallocateContext(int thread_num);
198 virtual void haltContext(int thread_num);
201 virtual void regStats();
202 virtual void resetStats();
204 // number of simulated instructions
206 Counter startNumInst;
207 Statistics::Formula numInsts;
209 // number of simulated memory references
210 Statistics::Scalar<> numMemRefs;
212 // number of simulated loads
214 Counter startNumLoad;
216 // number of idle cycles
217 Statistics::Average<> notIdleFraction;
218 Statistics::Formula idleFraction;
220 // number of cycles stalled for I-cache misses
221 Statistics::Scalar<> icacheStallCycles;
222 Counter lastIcacheStall;
224 // number of cycles stalled for D-cache misses
225 Statistics::Scalar<> dcacheStallCycles;
226 Counter lastDcacheStall;
228 void processCacheCompletion();
230 virtual void serialize(std::ostream &os);
231 virtual void unserialize(Checkpoint *cp, const std::string §ion);
234 Fault read(Addr addr, T &data, unsigned flags);
237 Fault write(T data, Addr addr, unsigned flags,
240 void prefetch(Addr addr, unsigned flags)
242 // need to do this...
245 void writeHint(Addr addr, int size)
247 // need to do this...
250 Fault copySrcTranslate(Addr src);
252 Fault copy(Addr dest);
254 uint64_t readIntReg(int reg_idx) { return xc->readIntReg(reg_idx); }
256 float readFloatRegSingle(int reg_idx)
257 { return xc->readFloatRegSingle(reg_idx); }
259 double readFloatRegDouble(int reg_idx)
260 { return xc->readFloatRegDouble(reg_idx); }
262 uint64_t readFloatRegInt(int reg_idx)
263 { return xc->readFloatRegInt(reg_idx); }
265 void setIntReg(int reg_idx, uint64_t val)
266 { return xc->setIntReg(reg_idx, val); }
268 void setFloatRegSingle(int reg_idx, float val)
269 { return xc->setFloatRegSingle(reg_idx, val); }
271 void setFloatRegDouble(int reg_idx, double val)
272 { return xc->setFloatRegDouble(reg_idx, val); }
274 void setFloatRegInt(int reg_idx, uint64_t val)
275 { return xc->setFloatRegInt(reg_idx, val); }
277 uint64_t readPC() { return xc->readPC(); }
278 void setNextPC(uint64_t val) { return xc->setNextPC(val); }
280 uint64_t readUniq() { return xc->readUniq(); }
281 void setUniq(uint64_t val) { return xc->setUniq(val); }
283 uint64_t readFpcr() { return xc->readFpcr(); }
284 void setFpcr(uint64_t val) { return xc->setFpcr(val); }
287 uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
288 Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
289 Fault hwrei() { return xc->hwrei(); }
290 int readIntrFlag() { return xc->readIntrFlag(); }
291 void setIntrFlag(int val) { xc->setIntrFlag(val); }
292 bool inPalMode() { return xc->inPalMode(); }
293 void ev5_trap(Fault fault) { return xc->ev5_trap(fault); }
294 bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
296 void syscall() { xc->syscall(); }
299 bool misspeculating() { return xc->misspeculating(); }
300 ExecContext *xcBase() { return xc; }
303 typedef SimpleCPU SimpleCPUExecContext;
305 #endif // __SIMPLE_CPU_HH__