2 * Copyright (c) 2003 The Regents of The University of Michigan
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29 #ifndef __SIMPLE_CPU_HH__
30 #define __SIMPLE_CPU_HH__
32 #include "cpu/base_cpu.hh"
33 #include "sim/eventq.hh"
34 #include "base/loader/symtab.hh"
35 #include "cpu/pc_event.hh"
36 #include "base/statistics.hh"
39 // forward declarations
58 class SimpleCPU : public BaseCPU
61 // main simulation loop (one cycle)
65 class TickEvent : public Event
71 TickEvent(SimpleCPU *c);
73 const char *description();
78 /// Schedule tick event, regardless of its current state.
79 void scheduleTickEvent(int delay)
81 if (tickEvent.squashed())
82 tickEvent.reschedule(curTick + delay);
83 else if (!tickEvent.scheduled())
84 tickEvent.schedule(curTick + delay);
87 /// Unschedule tick event, regardless of its current state.
88 void unscheduleTickEvent()
90 if (tickEvent.scheduled())
95 Trace::InstRecord *traceData;
97 void trace_data(T data) {
99 traceData->setData(data);
118 void post_interrupt(int int_num, int index);
120 void zero_fill_64(Addr addr) {
121 static int warned = 0;
123 warn ("WH64 is not implemented");
130 SimpleCPU(const std::string &_name,
132 Counter max_insts_any_thread, Counter max_insts_all_threads,
133 Counter max_loads_any_thread, Counter max_loads_all_threads,
134 AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
135 MemInterface *icache_interface, MemInterface *dcache_interface,
140 SimpleCPU(const std::string &_name, Process *_process,
141 Counter max_insts_any_thread,
142 Counter max_insts_all_threads,
143 Counter max_loads_any_thread,
144 Counter max_loads_all_threads,
145 MemInterface *icache_interface, MemInterface *dcache_interface);
149 virtual ~SimpleCPU();
155 void takeOverFrom(BaseCPU *oldCPU);
158 Addr dbg_vtophys(Addr addr);
163 // L1 instruction cache
164 MemInterface *icacheInterface;
167 MemInterface *dcacheInterface;
169 // current instruction
172 // Refcounted pointer to the one memory request.
175 class CacheCompletionEvent : public Event
181 CacheCompletionEvent(SimpleCPU *_cpu);
183 virtual void process();
184 virtual const char *description();
187 CacheCompletionEvent cacheCompletionEvent;
189 Status status() const { return _status; }
191 virtual void activateContext(int thread_num, int delay);
192 virtual void suspendContext(int thread_num);
193 virtual void deallocateContext(int thread_num);
194 virtual void haltContext(int thread_num);
197 virtual void regStats();
198 virtual void resetStats();
200 // number of simulated instructions
202 Counter startNumInst;
203 Statistics::Formula numInsts;
205 // number of simulated memory references
206 Statistics::Scalar<> numMemRefs;
208 // number of simulated loads
210 Counter startNumLoad;
212 // number of idle cycles
213 Statistics::Average<> notIdleFraction;
214 Statistics::Formula idleFraction;
216 // number of cycles stalled for I-cache misses
217 Statistics::Scalar<> icacheStallCycles;
218 Counter lastIcacheStall;
220 // number of cycles stalled for D-cache misses
221 Statistics::Scalar<> dcacheStallCycles;
222 Counter lastDcacheStall;
224 void processCacheCompletion();
226 virtual void serialize(std::ostream &os);
227 virtual void unserialize(Checkpoint *cp, const std::string §ion);
230 Fault read(Addr addr, T &data, unsigned flags);
233 Fault write(T data, Addr addr, unsigned flags,
236 Fault prefetch(Addr addr, unsigned flags)
238 // need to do this...
242 void writeHint(Addr addr, int size)
244 // need to do this...
248 #endif // __SIMPLE_CPU_HH__