cpu/simple_cpu/simple_cpu.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __SIMPLE_CPU_HH__
  30 #define __SIMPLE_CPU_HH__
  31
  32 #include "cpu/base_cpu.hh"
  33 #include "sim/eventq.hh"
  34 #include "base/loader/symtab.hh"
  35 #include "cpu/pc_event.hh"
  36 #include "base/statistics.hh"
  37
  38
  39 // forward declarations
  40 #ifdef FULL_SYSTEM
  41 class Processor;
  42 class Kernel;
  43 class AlphaItb;
  44 class AlphaDtb;
  45 class PhysicalMemory;
  46
  47 class RemoteGDB;
  48 class GDBListener;
  49 #endif // FULL_SYSTEM
  50
  51 class MemInterface;
  52 class Checkpoint;
  53
  54 namespace Trace {
  55     class InstRecord;
  56 }
  57
  58 class SimpleCPU : public BaseCPU
  59 {
  60   public:
  61     // main simulation loop (one cycle)
  62     void tick();
  63
  64   private:
  65     class TickEvent : public Event
  66     {
  67       private:
  68         SimpleCPU *cpu;
  69
  70       public:
  71         TickEvent(SimpleCPU *c);
  72         void process();
  73         const char *description();
  74     };
  75
  76     TickEvent tickEvent;
  77
  78     /// Schedule tick event, regardless of its current state.
  79     void scheduleTickEvent(int delay)
  80     {
  81         if (tickEvent.squashed())
  82             tickEvent.reschedule(curTick + delay);
  83         else if (!tickEvent.scheduled())
  84             tickEvent.schedule(curTick + delay);
  85     }
  86
  87     /// Unschedule tick event, regardless of its current state.
  88     void unscheduleTickEvent()
  89     {
  90         if (tickEvent.scheduled())
  91             tickEvent.squash();
  92     }
  93
  94   private:
  95     Trace::InstRecord *traceData;
  96     template<typename T>
  97     void trace_data(T data) {
  98       if (traceData) {
  99         traceData->setData(data);
 100       }
 101     };
 102
 103   public:
 104     //
 105     enum Status {
 106         Running,
 107         Idle,
 108         IcacheMissStall,
 109         IcacheMissComplete,
 110         DcacheMissStall,
 111         SwitchedOut
 112     };
 113
 114   private:
 115     Status _status;
 116
 117   public:
 118     void post_interrupt(int int_num, int index);
 119
 120     void zero_fill_64(Addr addr) {
 121       static int warned = 0;
 122       if (!warned) {
 123         warn ("WH64 is not implemented");
 124         warned = 1;
 125       }
 126     };
 127
 128 #ifdef FULL_SYSTEM
 129
 130     SimpleCPU(const std::string &_name,
 131               System *_system,
 132               Counter max_insts_any_thread, Counter max_insts_all_threads,
 133               Counter max_loads_any_thread, Counter max_loads_all_threads,
 134               AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
 135               MemInterface *icache_interface, MemInterface *dcache_interface,
 136               bool _def_reg, Tick freq);
 137
 138 #else
 139
 140     SimpleCPU(const std::string &_name, Process *_process,
 141               Counter max_insts_any_thread,
 142               Counter max_insts_all_threads,
 143               Counter max_loads_any_thread,
 144               Counter max_loads_all_threads,
 145               MemInterface *icache_interface, MemInterface *dcache_interface,
 146               bool _def_reg);
 147
 148 #endif
 149
 150     virtual ~SimpleCPU();
 151     virtual void init();
 152
 153     // execution context
 154     ExecContext *xc;
 155
 156     void switchOut();
 157     void takeOverFrom(BaseCPU *oldCPU);
 158
 159 #ifdef FULL_SYSTEM
 160     Addr dbg_vtophys(Addr addr);
 161
 162     bool interval_stats;
 163 #endif
 164
 165     // L1 instruction cache
 166     MemInterface *icacheInterface;
 167
 168     // L1 data cache
 169     MemInterface *dcacheInterface;
 170
 171     bool defer_registration;
 172
 173     // current instruction
 174     MachInst inst;
 175
 176     // Refcounted pointer to the one memory request.
 177     MemReqPtr memReq;
 178
 179     class CacheCompletionEvent : public Event
 180     {
 181       private:
 182         SimpleCPU *cpu;
 183
 184       public:
 185         CacheCompletionEvent(SimpleCPU *_cpu);
 186
 187         virtual void process();
 188         virtual const char *description();
 189     };
 190
 191     CacheCompletionEvent cacheCompletionEvent;
 192
 193     Status status() const { return _status; }
 194
 195     virtual void activateContext(int thread_num, int delay);
 196     virtual void suspendContext(int thread_num);
 197     virtual void deallocateContext(int thread_num);
 198     virtual void haltContext(int thread_num);
 199
 200     // statistics
 201     virtual void regStats();
 202     virtual void resetStats();
 203
 204     // number of simulated instructions
 205     Counter numInst;
 206     Counter startNumInst;
 207     Statistics::Formula numInsts;
 208
 209     // number of simulated memory references
 210     Statistics::Scalar<> numMemRefs;
 211
 212     // number of simulated loads
 213     Counter numLoad;
 214     Counter startNumLoad;
 215
 216     // number of idle cycles
 217     Statistics::Average<> notIdleFraction;
 218     Statistics::Formula idleFraction;
 219
 220     // number of cycles stalled for I-cache misses
 221     Statistics::Scalar<> icacheStallCycles;
 222     Counter lastIcacheStall;
 223
 224     // number of cycles stalled for D-cache misses
 225     Statistics::Scalar<> dcacheStallCycles;
 226     Counter lastDcacheStall;
 227
 228     void processCacheCompletion();
 229
 230     virtual void serialize(std::ostream &os);
 231     virtual void unserialize(Checkpoint *cp, const std::string &section);
 232
 233     template <class T>
 234     Fault read(Addr addr, T &data, unsigned flags);
 235
 236     template <class T>
 237     Fault write(T data, Addr addr, unsigned flags,
 238                         uint64_t *res);
 239
 240     Fault prefetch(Addr addr, unsigned flags)
 241     {
 242         // need to do this...
 243         return No_Fault;
 244     }
 245
 246     void writeHint(Addr addr, int size)
 247     {
 248         // need to do this...
 249     }
 250 };
 251
 252 #endif // __SIMPLE_CPU_HH__