cpu/simple_cpu/simple_cpu.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __SIMPLE_CPU_HH__
  30 #define __SIMPLE_CPU_HH__
  31
  32 #include "cpu/base_cpu.hh"
  33 #include "sim/eventq.hh"
  34 #include "base/loader/symtab.hh"
  35 #include "cpu/pc_event.hh"
  36 #include "base/statistics.hh"
  37
  38
  39 // forward declarations
  40 #ifdef FULL_SYSTEM
  41 class Processor;
  42 class Kernel;
  43 class AlphaItb;
  44 class AlphaDtb;
  45 class PhysicalMemory;
  46
  47 class RemoteGDB;
  48 class GDBListener;
  49 #endif // FULL_SYSTEM
  50
  51 class MemInterface;
  52 class IniFile;
  53
  54 namespace Trace {
  55     class InstRecord;
  56 }
  57
  58 class SimpleCPU : public BaseCPU
  59 {
  60   public:
  61     // main simulation loop (one cycle)
  62     void tick();
  63
  64   private:
  65     class TickEvent : public Event
  66     {
  67       private:
  68         SimpleCPU *cpu;
  69
  70       public:
  71         TickEvent(SimpleCPU *c)
  72             : Event(&mainEventQueue, 100), cpu(c) { }
  73         void process() { cpu->tick(); }
  74         virtual const char *description() { return "tick event"; }
  75     };
  76
  77     TickEvent tickEvent;
  78
  79   private:
  80     Trace::InstRecord *traceData;
  81     template<typename T>
  82     void trace_data(T data) {
  83       if (traceData) {
  84         traceData->setData(data);
  85       }
  86     };
  87
  88   public:
  89     //
  90     enum Status {
  91         Running,
  92         Idle,
  93         IcacheMissStall,
  94         IcacheMissComplete,
  95         DcacheMissStall,
  96         SwitchedOut
  97     };
  98
  99   private:
 100     Status _status;
 101
 102   public:
 103     void post_interrupt(int int_num, int index);
 104
 105     void zero_fill_64(Addr addr) {
 106       static int warned = 0;
 107       if (!warned) {
 108         warn ("WH64 is not implemented");
 109         warned = 1;
 110       }
 111     };
 112
 113 #ifdef FULL_SYSTEM
 114
 115     SimpleCPU(const std::string &_name,
 116               System *_system,
 117               Counter max_insts_any_thread, Counter max_insts_all_threads,
 118               Counter max_loads_any_thread, Counter max_loads_all_threads,
 119               AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
 120               MemInterface *icache_interface, MemInterface *dcache_interface,
 121               Tick freq);
 122
 123 #else
 124
 125     SimpleCPU(const std::string &_name, Process *_process,
 126               Counter max_insts_any_thread,
 127               Counter max_insts_all_threads,
 128               Counter max_loads_any_thread,
 129               Counter max_loads_all_threads,
 130               MemInterface *icache_interface, MemInterface *dcache_interface);
 131
 132 #endif
 133
 134     virtual ~SimpleCPU();
 135
 136     // execution context
 137     ExecContext *xc;
 138
 139     void switchOut();
 140     void takeOverFrom(BaseCPU *oldCPU);
 141
 142 #ifdef FULL_SYSTEM
 143     Addr dbg_vtophys(Addr addr);
 144
 145     bool interval_stats;
 146 #endif
 147
 148     // L1 instruction cache
 149     MemInterface *icacheInterface;
 150
 151     // L1 data cache
 152     MemInterface *dcacheInterface;
 153
 154     // current instruction
 155     MachInst inst;
 156
 157     // current fault status
 158     Fault fault;
 159
 160     // Refcounted pointer to the one memory request.
 161     MemReqPtr memReq;
 162
 163     class CacheCompletionEvent : public Event
 164     {
 165       private:
 166         SimpleCPU *cpu;
 167
 168       public:
 169         CacheCompletionEvent(SimpleCPU *_cpu);
 170
 171         virtual void process();
 172         virtual const char *description();
 173     };
 174
 175     CacheCompletionEvent cacheCompletionEvent;
 176
 177     Status status() const { return _status; }
 178
 179     virtual void execCtxStatusChg(int thread_num);
 180
 181     void setStatus(Status new_status) {
 182         Status old_status = status();
 183
 184         // We should never even get here if the CPU has been switched out.
 185         assert(old_status != SwitchedOut);
 186
 187         _status = new_status;
 188
 189         switch (status()) {
 190           case IcacheMissStall:
 191             assert(old_status == Running);
 192             lastIcacheStall = curTick;
 193             if (tickEvent.scheduled())
 194                 tickEvent.squash();
 195             break;
 196
 197           case IcacheMissComplete:
 198             assert(old_status == IcacheMissStall);
 199             if (tickEvent.squashed())
 200                 tickEvent.reschedule(curTick + 1);
 201             else if (!tickEvent.scheduled())
 202                 tickEvent.schedule(curTick + 1);
 203             break;
 204
 205           case DcacheMissStall:
 206             assert(old_status == Running);
 207             lastDcacheStall = curTick;
 208             if (tickEvent.scheduled())
 209                 tickEvent.squash();
 210             break;
 211
 212           case Idle:
 213             assert(old_status == Running);
 214             last_idle = curTick;
 215             if (tickEvent.scheduled())
 216                 tickEvent.squash();
 217             break;
 218
 219           case Running:
 220             assert(old_status == Idle ||
 221                    old_status == DcacheMissStall ||
 222                    old_status == IcacheMissComplete);
 223             if (old_status == Idle)
 224                 idleCycles += curTick - last_idle;
 225
 226             if (tickEvent.squashed())
 227                 tickEvent.reschedule(curTick + 1);
 228             else if (!tickEvent.scheduled())
 229                 tickEvent.schedule(curTick + 1);
 230             break;
 231
 232           default:
 233             panic("can't get here");
 234         }
 235     }
 236
 237     // statistics
 238     void regStats();
 239
 240     // number of simulated instructions
 241     Counter numInst;
 242     Statistics::Formula numInsts;
 243
 244     // number of simulated memory references
 245     Statistics::Scalar<> numMemRefs;
 246
 247     // number of simulated loads
 248     Counter numLoad;
 249
 250     // number of idle cycles
 251     Statistics::Scalar<> idleCycles;
 252     Statistics::Formula idleFraction;
 253     Counter last_idle;
 254
 255     // number of cycles stalled for I-cache misses
 256     Statistics::Scalar<> icacheStallCycles;
 257     Counter lastIcacheStall;
 258
 259     // number of cycles stalled for D-cache misses
 260     Statistics::Scalar<> dcacheStallCycles;
 261     Counter lastDcacheStall;
 262
 263     void processCacheCompletion();
 264
 265     virtual void serialize();
 266     virtual void unserialize(IniFile &db, const std::string &category,
 267                              ConfigNode *node);
 268
 269     template <class T>
 270     Fault read(Addr addr, T& data, unsigned flags);
 271
 272     template <class T>
 273     Fault write(T data, Addr addr, unsigned flags,
 274                         uint64_t *res);
 275
 276     Fault prefetch(Addr addr, unsigned flags)
 277     {
 278         // need to do this...
 279         return No_Fault;
 280     }
 281
 282     void writeHint(Addr addr, int size)
 283     {
 284         // need to do this...
 285     }
 286 };
 287
 288 #endif // __SIMPLE_CPU_HH__