cpu/simple_cpu/simple_cpu.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __SIMPLE_CPU_HH__
  30 #define __SIMPLE_CPU_HH__
  31
  32 #include "cpu/base_cpu.hh"
  33 #include "sim/eventq.hh"
  34 #include "base/loader/symtab.hh"
  35 #include "cpu/pc_event.hh"
  36 #include "base/statistics.hh"
  37 #include "cpu/exec_context.hh"
  38 #include "cpu/static_inst.hh"
  39
  40 // forward declarations
  41 #ifdef FULL_SYSTEM
  42 class Processor;
  43 class Kernel;
  44 class AlphaITB;
  45 class AlphaDTB;
  46 class PhysicalMemory;
  47
  48 class RemoteGDB;
  49 class GDBListener;
  50
  51 #else
  52
  53 class Process;
  54
  55 #endif // FULL_SYSTEM
  56
  57 class MemInterface;
  58 class Checkpoint;
  59
  60 namespace Trace {
  61     class InstRecord;
  62 }
  63
  64 class SimpleCPU : public BaseCPU
  65 {
  66   public:
  67     // main simulation loop (one cycle)
  68     void tick();
  69
  70   private:
  71     class TickEvent : public Event
  72     {
  73       private:
  74         SimpleCPU *cpu;
  75
  76       public:
  77         TickEvent(SimpleCPU *c);
  78         void process();
  79         const char *description();
  80     };
  81
  82     TickEvent tickEvent;
  83
  84     /// Schedule tick event, regardless of its current state.
  85     void scheduleTickEvent(int delay)
  86     {
  87         if (tickEvent.squashed())
  88             tickEvent.reschedule(curTick + delay);
  89         else if (!tickEvent.scheduled())
  90             tickEvent.schedule(curTick + delay);
  91     }
  92
  93     /// Unschedule tick event, regardless of its current state.
  94     void unscheduleTickEvent()
  95     {
  96         if (tickEvent.scheduled())
  97             tickEvent.squash();
  98     }
  99
 100   private:
 101     Trace::InstRecord *traceData;
 102     template<typename T>
 103     void trace_data(T data) {
 104       if (traceData) {
 105         traceData->setData(data);
 106       }
 107     };
 108
 109   public:
 110     //
 111     enum Status {
 112         Running,
 113         Idle,
 114         IcacheMissStall,
 115         IcacheMissComplete,
 116         DcacheMissStall,
 117         SwitchedOut
 118     };
 119
 120   private:
 121     Status _status;
 122
 123   public:
 124     void post_interrupt(int int_num, int index);
 125
 126     void zero_fill_64(Addr addr) {
 127       static int warned = 0;
 128       if (!warned) {
 129         warn ("WH64 is not implemented");
 130         warned = 1;
 131       }
 132     };
 133
 134 #ifdef FULL_SYSTEM
 135
 136     SimpleCPU(const std::string &_name,
 137               System *_system,
 138               Counter max_insts_any_thread, Counter max_insts_all_threads,
 139               Counter max_loads_any_thread, Counter max_loads_all_threads,
 140               AlphaITB *itb, AlphaDTB *dtb, FunctionalMemory *mem,
 141               MemInterface *icache_interface, MemInterface *dcache_interface,
 142               bool _def_reg, Tick freq);
 143
 144 #else
 145
 146     SimpleCPU(const std::string &_name, Process *_process,
 147               Counter max_insts_any_thread,
 148               Counter max_insts_all_threads,
 149               Counter max_loads_any_thread,
 150               Counter max_loads_all_threads,
 151               MemInterface *icache_interface, MemInterface *dcache_interface,
 152               bool _def_reg);
 153
 154 #endif
 155
 156     virtual ~SimpleCPU();
 157     virtual void init();
 158
 159     // execution context
 160     ExecContext *xc;
 161
 162     void switchOut();
 163     void takeOverFrom(BaseCPU *oldCPU);
 164
 165 #ifdef FULL_SYSTEM
 166     Addr dbg_vtophys(Addr addr);
 167
 168     bool interval_stats;
 169 #endif
 170
 171     // L1 instruction cache
 172     MemInterface *icacheInterface;
 173
 174     // L1 data cache
 175     MemInterface *dcacheInterface;
 176
 177     bool defer_registration;
 178
 179     // current instruction
 180     MachInst inst;
 181
 182     // Refcounted pointer to the one memory request.
 183     MemReqPtr memReq;
 184
 185     class CacheCompletionEvent : public Event
 186     {
 187       private:
 188         SimpleCPU *cpu;
 189
 190       public:
 191         CacheCompletionEvent(SimpleCPU *_cpu);
 192
 193         virtual void process();
 194         virtual const char *description();
 195     };
 196
 197     CacheCompletionEvent cacheCompletionEvent;
 198
 199     Status status() const { return _status; }
 200
 201     virtual void activateContext(int thread_num, int delay);
 202     virtual void suspendContext(int thread_num);
 203     virtual void deallocateContext(int thread_num);
 204     virtual void haltContext(int thread_num);
 205
 206     // statistics
 207     virtual void regStats();
 208     virtual void resetStats();
 209
 210     // number of simulated instructions
 211     Counter numInst;
 212     Counter startNumInst;
 213     Stats::Scalar<> numInsts;
 214
 215     virtual Counter totalInstructions() const
 216     {
 217         return numInst - startNumInst;
 218     }
 219
 220     // number of simulated memory references
 221     Stats::Scalar<> numMemRefs;
 222
 223     // number of simulated loads
 224     Counter numLoad;
 225     Counter startNumLoad;
 226
 227     // number of idle cycles
 228     Stats::Average<> notIdleFraction;
 229     Stats::Formula idleFraction;
 230
 231     // number of cycles stalled for I-cache misses
 232     Stats::Scalar<> icacheStallCycles;
 233     Counter lastIcacheStall;
 234
 235     // number of cycles stalled for D-cache misses
 236     Stats::Scalar<> dcacheStallCycles;
 237     Counter lastDcacheStall;
 238
 239     void processCacheCompletion();
 240
 241     virtual void serialize(std::ostream &os);
 242     virtual void unserialize(Checkpoint *cp, const std::string &section);
 243
 244     template <class T>
 245     Fault read(Addr addr, T &data, unsigned flags);
 246
 247     template <class T>
 248     Fault write(T data, Addr addr, unsigned flags,
 249                         uint64_t *res);
 250
 251     void prefetch(Addr addr, unsigned flags)
 252     {
 253         // need to do this...
 254     }
 255
 256     void writeHint(Addr addr, int size)
 257     {
 258         // need to do this...
 259     }
 260
 261     Fault copySrcTranslate(Addr src);
 262
 263     Fault copy(Addr dest);
 264
 265     // The register accessor methods provide the index of the
 266     // instruction's operand (e.g., 0 or 1), not the architectural
 267     // register index, to simplify the implementation of register
 268     // renaming.  We find the architectural register index by indexing
 269     // into the instruction's own operand index table.  Note that a
 270     // raw pointer to the StaticInst is provided instead of a
 271     // ref-counted StaticInstPtr to redice overhead.  This is fine as
 272     // long as these methods don't copy the pointer into any long-term
 273     // storage (which is pretty hard to imagine they would have reason
 274     // to do).
 275
 276     uint64_t readIntReg(StaticInst<TheISA> *si, int idx)
 277     {
 278         return xc->readIntReg(si->srcRegIdx(idx));
 279     }
 280
 281     float readFloatRegSingle(StaticInst<TheISA> *si, int idx)
 282     {
 283         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 284         return xc->readFloatRegSingle(reg_idx);
 285     }
 286
 287     double readFloatRegDouble(StaticInst<TheISA> *si, int idx)
 288     {
 289         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 290         return xc->readFloatRegDouble(reg_idx);
 291     }
 292
 293     uint64_t readFloatRegInt(StaticInst<TheISA> *si, int idx)
 294     {
 295         int reg_idx = si->srcRegIdx(idx) - TheISA::FP_Base_DepTag;
 296         return xc->readFloatRegInt(reg_idx);
 297     }
 298
 299     void setIntReg(StaticInst<TheISA> *si, int idx, uint64_t val)
 300     {
 301         xc->setIntReg(si->destRegIdx(idx), val);
 302     }
 303
 304     void setFloatRegSingle(StaticInst<TheISA> *si, int idx, float val)
 305     {
 306         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 307         xc->setFloatRegSingle(reg_idx, val);
 308     }
 309
 310     void setFloatRegDouble(StaticInst<TheISA> *si, int idx, double val)
 311     {
 312         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 313         xc->setFloatRegDouble(reg_idx, val);
 314     }
 315
 316     void setFloatRegInt(StaticInst<TheISA> *si, int idx, uint64_t val)
 317     {
 318         int reg_idx = si->destRegIdx(idx) - TheISA::FP_Base_DepTag;
 319         xc->setFloatRegInt(reg_idx, val);
 320     }
 321
 322     uint64_t readPC() { return xc->readPC(); }
 323     void setNextPC(uint64_t val) { xc->setNextPC(val); }
 324
 325     uint64_t readUniq() { return xc->readUniq(); }
 326     void setUniq(uint64_t val) { xc->setUniq(val); }
 327
 328     uint64_t readFpcr() { return xc->readFpcr(); }
 329     void setFpcr(uint64_t val) { xc->setFpcr(val); }
 330
 331 #ifdef FULL_SYSTEM
 332     uint64_t readIpr(int idx, Fault &fault) { return xc->readIpr(idx, fault); }
 333     Fault setIpr(int idx, uint64_t val) { return xc->setIpr(idx, val); }
 334     Fault hwrei() { return xc->hwrei(); }
 335     int readIntrFlag() { return xc->readIntrFlag(); }
 336     void setIntrFlag(int val) { xc->setIntrFlag(val); }
 337     bool inPalMode() { return xc->inPalMode(); }
 338     void ev5_trap(Fault fault) { xc->ev5_trap(fault); }
 339     bool simPalCheck(int palFunc) { return xc->simPalCheck(palFunc); }
 340 #else
 341     void syscall() { xc->syscall(); }
 342 #endif
 343
 344     bool misspeculating() { return xc->misspeculating(); }
 345     ExecContext *xcBase() { return xc; }
 346 };
 347
 348 #endif // __SIMPLE_CPU_HH__