cpu/simple_cpu/simple_cpu.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __SIMPLE_CPU_HH__
  30 #define __SIMPLE_CPU_HH__
  31
  32 #include "cpu/base_cpu.hh"
  33 #include "sim/eventq.hh"
  34 #include "base/loader/symtab.hh"
  35 #include "cpu/pc_event.hh"
  36 #include "base/statistics.hh"
  37
  38
  39 // forward declarations
  40 #ifdef FULL_SYSTEM
  41 class Processor;
  42 class Kernel;
  43 class AlphaItb;
  44 class AlphaDtb;
  45 class PhysicalMemory;
  46
  47 class RemoteGDB;
  48 class GDBListener;
  49 #endif // FULL_SYSTEM
  50
  51 class MemInterface;
  52 class IniFile;
  53
  54 namespace Trace {
  55     class InstRecord;
  56 }
  57
  58 class SimpleCPU : public BaseCPU
  59 {
  60   public:
  61     // main simulation loop (one cycle)
  62     void tick();
  63
  64   private:
  65     class TickEvent : public Event
  66     {
  67       private:
  68         SimpleCPU *cpu;
  69
  70       public:
  71         TickEvent(SimpleCPU *c)
  72             : Event(&mainEventQueue, 100), cpu(c) { }
  73         void process() { cpu->tick(); }
  74         virtual const char *description() { return "tick event"; }
  75     };
  76
  77     TickEvent tickEvent;
  78
  79   private:
  80     Trace::InstRecord *traceData;
  81     template<typename T>
  82     void trace_data(T data) {
  83       if (traceData) {
  84         traceData->setData(data);
  85       }
  86     };
  87
  88   public:
  89     //
  90     enum Status {
  91         Running,
  92         Idle,
  93         IcacheMissStall,
  94         IcacheMissComplete,
  95         DcacheMissStall,
  96         SwitchedOut
  97     };
  98
  99   private:
 100     Status _status;
 101
 102   public:
 103     void post_interrupt(int int_num, int index);
 104
 105     void zero_fill_64(Addr addr) {
 106       static int warned = 0;
 107       if (!warned) {
 108         warn ("WH64 is not implemented");
 109         warned = 1;
 110       }
 111     };
 112
 113 #ifdef FULL_SYSTEM
 114
 115     SimpleCPU(const std::string &_name,
 116               System *_system,
 117               Counter max_insts_any_thread, Counter max_insts_all_threads,
 118               Counter max_loads_any_thread, Counter max_loads_all_threads,
 119               AlphaItb *itb, AlphaDtb *dtb, FunctionalMemory *mem,
 120               MemInterface *icache_interface, MemInterface *dcache_interface,
 121               Tick freq);
 122
 123 #else
 124
 125     SimpleCPU(const std::string &_name, Process *_process,
 126               Counter max_insts_any_thread,
 127               Counter max_insts_all_threads,
 128               Counter max_loads_any_thread,
 129               Counter max_loads_all_threads,
 130               MemInterface *icache_interface, MemInterface *dcache_interface);
 131
 132 #endif
 133
 134     virtual ~SimpleCPU();
 135
 136     // execution context
 137     ExecContext *xc;
 138
 139     void switchOut();
 140     void takeOverFrom(BaseCPU *oldCPU);
 141
 142 #ifdef FULL_SYSTEM
 143     Addr dbg_vtophys(Addr addr);
 144
 145     bool interval_stats;
 146 #endif
 147
 148     // L1 instruction cache
 149     MemInterface *icacheInterface;
 150
 151     // L1 data cache
 152     MemInterface *dcacheInterface;
 153
 154     // current instruction
 155     MachInst inst;
 156
 157     // Refcounted pointer to the one memory request.
 158     MemReqPtr memReq;
 159
 160     class CacheCompletionEvent : public Event
 161     {
 162       private:
 163         SimpleCPU *cpu;
 164
 165       public:
 166         CacheCompletionEvent(SimpleCPU *_cpu);
 167
 168         virtual void process();
 169         virtual const char *description();
 170     };
 171
 172     CacheCompletionEvent cacheCompletionEvent;
 173
 174     Status status() const { return _status; }
 175
 176     virtual void execCtxStatusChg(int thread_num);
 177
 178     void setStatus(Status new_status) {
 179         Status old_status = status();
 180
 181         // We should never even get here if the CPU has been switched out.
 182         assert(old_status != SwitchedOut);
 183
 184         _status = new_status;
 185
 186         switch (status()) {
 187           case IcacheMissStall:
 188             assert(old_status == Running);
 189             lastIcacheStall = curTick;
 190             if (tickEvent.scheduled())
 191                 tickEvent.squash();
 192             break;
 193
 194           case IcacheMissComplete:
 195             assert(old_status == IcacheMissStall);
 196             if (tickEvent.squashed())
 197                 tickEvent.reschedule(curTick + 1);
 198             else if (!tickEvent.scheduled())
 199                 tickEvent.schedule(curTick + 1);
 200             break;
 201
 202           case DcacheMissStall:
 203             assert(old_status == Running);
 204             lastDcacheStall = curTick;
 205             if (tickEvent.scheduled())
 206                 tickEvent.squash();
 207             break;
 208
 209           case Idle:
 210             assert(old_status == Running);
 211             last_idle = curTick;
 212             if (tickEvent.scheduled())
 213                 tickEvent.squash();
 214             break;
 215
 216           case Running:
 217             assert(old_status == Idle ||
 218                    old_status == DcacheMissStall ||
 219                    old_status == IcacheMissComplete);
 220             if (old_status == Idle)
 221                 idleCycles += curTick - last_idle;
 222
 223             if (tickEvent.squashed())
 224                 tickEvent.reschedule(curTick + 1);
 225             else if (!tickEvent.scheduled())
 226                 tickEvent.schedule(curTick + 1);
 227             break;
 228
 229           default:
 230             panic("can't get here");
 231         }
 232     }
 233
 234     // statistics
 235     void regStats();
 236
 237     // number of simulated instructions
 238     Counter numInst;
 239     Statistics::Formula numInsts;
 240
 241     // number of simulated memory references
 242     Statistics::Scalar<> numMemRefs;
 243
 244     // number of simulated loads
 245     Counter numLoad;
 246
 247     // number of idle cycles
 248     Statistics::Scalar<> idleCycles;
 249     Statistics::Formula idleFraction;
 250     Counter last_idle;
 251
 252     // number of cycles stalled for I-cache misses
 253     Statistics::Scalar<> icacheStallCycles;
 254     Counter lastIcacheStall;
 255
 256     // number of cycles stalled for D-cache misses
 257     Statistics::Scalar<> dcacheStallCycles;
 258     Counter lastDcacheStall;
 259
 260     void processCacheCompletion();
 261
 262     virtual void serialize(std::ostream &os);
 263     virtual void unserialize(IniFile &db, const std::string &section);
 264
 265     template <class T>
 266     Fault read(Addr addr, T& data, unsigned flags);
 267
 268     template <class T>
 269     Fault write(T data, Addr addr, unsigned flags,
 270                         uint64_t *res);
 271
 272     Fault prefetch(Addr addr, unsigned flags)
 273     {
 274         // need to do this...
 275         return No_Fault;
 276     }
 277
 278     void writeHint(Addr addr, int size)
 279     {
 280         // need to do this...
 281     }
 282 };
 283
 284 #endif // __SIMPLE_CPU_HH__