cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __CPU_STATIC_INST_HH__
  30 #define __CPU_STATIC_INST_HH__
  31
  32 #include <bitset>
  33 #include <string>
  34
  35 #include "base/hashmap.hh"
  36 #include "base/refcnt.hh"
  37 #include "encumbered/cpu/full/op_class.hh"
  38 #include "sim/host.hh"
  39 #include "arch/isa_traits.hh"
  40
  41 // forward declarations
  42 struct AlphaSimpleImpl;
  43 class ExecContext;
  44 class DynInst;
  45
  46 template <class Impl>
  47 class AlphaDynInst;
  48
  49 class FastCPU;
  50 class SimpleCPU;
  51 class InorderCPU;
  52 class SymbolTable;
  53
  54 namespace Trace {
  55     class InstRecord;
  56 }
  57
  58 /**
  59  * Base, ISA-independent static instruction class.
  60  *
  61  * The main component of this class is the vector of flags and the
  62  * associated methods for reading them.  Any object that can rely
  63  * solely on these flags can process instructions without being
  64  * recompiled for multiple ISAs.
  65  */
  66 class StaticInstBase : public RefCounted
  67 {
  68   protected:
  69
  70     /// Set of boolean static instruction properties.
  71     ///
  72     /// Notes:
  73     /// - The IsInteger and IsFloating flags are based on the class of
  74     /// registers accessed by the instruction.  Although most
  75     /// instructions will have exactly one of these two flags set, it
  76     /// is possible for an instruction to have neither (e.g., direct
  77     /// unconditional branches, memory barriers) or both (e.g., an
  78     /// FP/int conversion).
  79     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  80     /// will be set.
  81     /// - If IsControl is set, then exactly one of IsDirectControl or
  82     /// IsIndirect Control will be set, and exactly one of
  83     /// IsCondControl or IsUncondControl will be set.
  84     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
  85     /// implemented as flags since in the current model there's no
  86     /// other way for instructions to inject behavior into the
  87     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
  88     /// model we should be able to get rid of these flags and
  89     /// implement this behavior via the execute() methods.
  90     ///
  91     enum Flags {
  92         IsNop,          ///< Is a no-op (no effect at all).
  93
  94         IsInteger,      ///< References integer regs.
  95         IsFloating,     ///< References FP regs.
  96
  97         IsMemRef,       ///< References memory (load, store, or prefetch).
  98         IsLoad,         ///< Reads from memory (load or prefetch).
  99         IsStore,        ///< Writes to memory.
 100         IsInstPrefetch, ///< Instruction-cache prefetch.
 101         IsDataPrefetch, ///< Data-cache prefetch.
 102         IsCopy,         ///< Fast Cache block copy
 103
 104         IsControl,              ///< Control transfer instruction.
 105         IsDirectControl,        ///< PC relative control transfer.
 106         IsIndirectControl,      ///< Register indirect control transfer.
 107         IsCondControl,          ///< Conditional control transfer.
 108         IsUncondControl,        ///< Unconditional control transfer.
 109         IsCall,                 ///< Subroutine call.
 110         IsReturn,               ///< Subroutine return.
 111
 112         IsThreadSync,   ///< Thread synchronization operation.
 113
 114         IsSerializing,  ///< Serializes pipeline: won't execute until all
 115                         /// older instructions have committed.
 116         IsMemBarrier,   ///< Is a memory barrier
 117         IsWriteBarrier, ///< Is a write barrier
 118
 119         IsNonSpeculative, ///< Should not be executed speculatively
 120
 121         NumFlags
 122     };
 123
 124     /// Flag values for this instruction.
 125     std::bitset<NumFlags> flags;
 126
 127     /// See opClass().
 128     OpClass _opClass;
 129
 130     /// See numSrcRegs().
 131     int8_t _numSrcRegs;
 132
 133     /// See numDestRegs().
 134     int8_t _numDestRegs;
 135
 136     /// The following are used to track physical register usage
 137     /// for machines with separate int & FP reg files.
 138     //@{
 139     int8_t _numFPDestRegs;
 140     int8_t _numIntDestRegs;
 141     //@}
 142
 143     /// Constructor.
 144     /// It's important to initialize everything here to a sane
 145     /// default, since the decoder generally only overrides
 146     /// the fields that are meaningful for the particular
 147     /// instruction.
 148     StaticInstBase(OpClass __opClass)
 149         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 150           _numFPDestRegs(0), _numIntDestRegs(0)
 151     {
 152     }
 153
 154   public:
 155
 156     /// @name Register information.
 157     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 158     /// numDestRegs().  The former two functions are used to track
 159     /// physical register usage for machines with separate int & FP
 160     /// reg files.
 161     //@{
 162     /// Number of source registers.
 163     int8_t numSrcRegs()  const { return _numSrcRegs; }
 164     /// Number of destination registers.
 165     int8_t numDestRegs() const { return _numDestRegs; }
 166     /// Number of floating-point destination regs.
 167     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 168     /// Number of integer destination regs.
 169     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 170     //@}
 171
 172     /// @name Flag accessors.
 173     /// These functions are used to access the values of the various
 174     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 175     /// of the individual flags.
 176     //@{
 177
 178     bool isNop()          const { return flags[IsNop]; }
 179
 180     bool isMemRef()       const { return flags[IsMemRef]; }
 181     bool isLoad()         const { return flags[IsLoad]; }
 182     bool isStore()        const { return flags[IsStore]; }
 183     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 184     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 185     bool isCopy()         const { return flags[IsCopy];}
 186
 187     bool isInteger()      const { return flags[IsInteger]; }
 188     bool isFloating()     const { return flags[IsFloating]; }
 189
 190     bool isControl()      const { return flags[IsControl]; }
 191     bool isCall()         const { return flags[IsCall]; }
 192     bool isReturn()       const { return flags[IsReturn]; }
 193     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 194     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 195     bool isCondCtrl()     const { return flags[IsCondControl]; }
 196     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 197
 198     bool isThreadSync()   const { return flags[IsThreadSync]; }
 199     bool isSerializing()  const { return flags[IsSerializing]; }
 200     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 201     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 202     bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
 203     //@}
 204
 205     /// Operation class.  Used to select appropriate function unit in issue.
 206     OpClass opClass()     const { return _opClass; }
 207 };
 208
 209
 210 // forward declaration
 211 template <class ISA>
 212 class StaticInstPtr;
 213
 214 /**
 215  * Generic yet ISA-dependent static instruction class.
 216  *
 217  * This class builds on StaticInstBase, defining fields and interfaces
 218  * that are generic across all ISAs but that differ in details
 219  * according to the specific ISA being used.
 220  */
 221 template <class ISA>
 222 class StaticInst : public StaticInstBase
 223 {
 224   public:
 225
 226     /// Binary machine instruction type.
 227     typedef typename ISA::MachInst MachInst;
 228     /// Memory address type.
 229     typedef typename ISA::Addr     Addr;
 230     /// Logical register index type.
 231     typedef typename ISA::RegIndex RegIndex;
 232
 233     enum {
 234         MaxInstSrcRegs = ISA::MaxInstSrcRegs,   //< Max source regs
 235         MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
 236     };
 237
 238
 239     /// Return logical index (architectural reg num) of i'th destination reg.
 240     /// Only the entries from 0 through numDestRegs()-1 are valid.
 241     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 242
 243     /// Return logical index (architectural reg num) of i'th source reg.
 244     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 245     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 246
 247     /// Pointer to a statically allocated "null" instruction object.
 248     /// Used to give eaCompInst() and memAccInst() something to return
 249     /// when called on non-memory instructions.
 250     static StaticInstPtr<ISA> nullStaticInstPtr;
 251
 252     /**
 253      * Memory references only: returns "fake" instruction representing
 254      * the effective address part of the memory operation.  Used to
 255      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 256      * just the EA computation.
 257      */
 258     virtual const
 259     StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
 260
 261     /**
 262      * Memory references only: returns "fake" instruction representing
 263      * the memory access part of the memory operation.  Used to
 264      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 265      * just the memory access (not the EA computation).
 266      */
 267     virtual const
 268     StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
 269
 270     /// The binary machine instruction.
 271     const MachInst machInst;
 272
 273   protected:
 274
 275     /// See destRegIdx().
 276     RegIndex _destRegIdx[MaxInstDestRegs];
 277     /// See srcRegIdx().
 278     RegIndex _srcRegIdx[MaxInstSrcRegs];
 279
 280     /**
 281      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 282      * methods.  Also useful to readily identify instructions from
 283      * within the debugger when #cachedDisassembly has not been
 284      * initialized.
 285      */
 286     const char *mnemonic;
 287
 288     /**
 289      * String representation of disassembly (lazily evaluated via
 290      * disassemble()).
 291      */
 292     mutable std::string *cachedDisassembly;
 293
 294     /**
 295      * Internal function to generate disassembly string.
 296      */
 297     virtual std::string
 298     generateDisassembly(Addr pc, const SymbolTable *symtab) const = 0;
 299
 300     /// Constructor.
 301     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
 302         : StaticInstBase(__opClass),
 303           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 304     {
 305     }
 306
 307   public:
 308
 309     virtual ~StaticInst()
 310     {
 311         if (cachedDisassembly)
 312             delete cachedDisassembly;
 313     }
 314
 315 #include "static_inst_impl.hh"
 316
 317     /**
 318      * Return the target address for a PC-relative branch.
 319      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 320      * should be true).
 321      */
 322     virtual Addr branchTarget(Addr branchPC) const
 323     {
 324         panic("StaticInst::branchTarget() called on instruction "
 325               "that is not a PC-relative branch.");
 326     }
 327
 328     /**
 329      * Return the target address for an indirect branch (jump).  The
 330      * register value is read from the supplied execution context, so
 331      * the result is valid only if the execution context is about to
 332      * execute the branch in question.  Invalid if not an indirect
 333      * branch (i.e. isIndirectCtrl() should be true).
 334      */
 335     virtual Addr branchTarget(ExecContext *xc) const
 336     {
 337         panic("StaticInst::branchTarget() called on instruction "
 338               "that is not an indirect branch.");
 339     }
 340
 341     /**
 342      * Return true if the instruction is a control transfer, and if so,
 343      * return the target address as well.
 344      */
 345     bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt) const;
 346
 347     /**
 348      * Return string representation of disassembled instruction.
 349      * The default version of this function will call the internal
 350      * virtual generateDisassembly() function to get the string,
 351      * then cache it in #cachedDisassembly.  If the disassembly
 352      * should not be cached, this function should be overridden directly.
 353      */
 354     virtual const std::string &disassemble(Addr pc,
 355                                            const SymbolTable *symtab = 0) const
 356     {
 357         if (!cachedDisassembly)
 358             cachedDisassembly =
 359                 new std::string(generateDisassembly(pc, symtab));
 360
 361         return *cachedDisassembly;
 362     }
 363
 364     /// Decoded instruction cache type.
 365     /// For now we're using a generic hash_map; this seems to work
 366     /// pretty well.
 367     typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
 368
 369     /// A cache of decoded instruction objects.
 370     static DecodeCache decodeCache;
 371
 372     /**
 373      * Dump some basic stats on the decode cache hash map.
 374      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 375      */
 376     static void dumpDecodeCacheStats();
 377
 378     /// Decode a machine instruction.
 379     /// @param mach_inst The binary instruction to decode.
 380     /// @retval A pointer to the corresponding StaticInst object.
 381     static
 382     StaticInstPtr<ISA> decode(MachInst mach_inst)
 383     {
 384 #ifdef DECODE_CACHE_HASH_STATS
 385         // Simple stats on decode hash_map.  Turns out the default
 386         // hash function is as good as anything I could come up with.
 387         const int dump_every_n = 10000000;
 388         static int decodes_til_dump = dump_every_n;
 389
 390         if (--decodes_til_dump == 0) {
 391             dumpDecodeCacheStats();
 392             decodes_til_dump = dump_every_n;
 393         }
 394 #endif
 395
 396         typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
 397         if (iter != decodeCache.end()) {
 398             return iter->second;
 399         }
 400
 401         StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
 402         decodeCache[mach_inst] = si;
 403         return si;
 404     }
 405 };
 406
 407 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 408
 409 /// Reference-counted pointer to a StaticInst object.
 410 /// This type should be used instead of "StaticInst<ISA> *" so that
 411 /// StaticInst objects can be properly reference-counted.
 412 template <class ISA>
 413 class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
 414 {
 415   public:
 416     /// Constructor.
 417     StaticInstPtr()
 418         : RefCountingPtr<StaticInst<ISA> >()
 419     {
 420     }
 421
 422     /// Conversion from "StaticInst<ISA> *".
 423     StaticInstPtr(StaticInst<ISA> *p)
 424         : RefCountingPtr<StaticInst<ISA> >(p)
 425     {
 426     }
 427
 428     /// Copy constructor.
 429     StaticInstPtr(const StaticInstPtr &r)
 430         : RefCountingPtr<StaticInst<ISA> >(r)
 431     {
 432     }
 433
 434     /// Construct directly from machine instruction.
 435     /// Calls StaticInst<ISA>::decode().
 436     StaticInstPtr(typename ISA::MachInst mach_inst)
 437         : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
 438     {
 439     }
 440
 441     /// Convert to pointer to StaticInstBase class.
 442     operator const StaticInstBasePtr()
 443     {
 444         return this->get();
 445     }
 446 };
 447
 448 #endif // __CPU_STATIC_INST_HH__