cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __STATIC_INST_HH__
  30 #define __STATIC_INST_HH__
  31
  32 #include <bitset>
  33 #include <string>
  34
  35 #include "sim/host.hh"
  36 #include "base/hashmap.hh"
  37 #include "base/refcnt.hh"
  38
  39 #include "cpu/full_cpu/op_class.hh"
  40 #include "targetarch/isa_traits.hh"
  41
  42 // forward declarations
  43 class ExecContext;
  44 class SpecExecContext;
  45 class SimpleCPU;
  46 class FullCPU;
  47 class DynInst;
  48 class SymbolTable;
  49
  50 namespace Trace {
  51     class InstRecord;
  52 }
  53
  54 /**
  55  * Base, ISA-independent static instruction class.
  56  *
  57  * The main component of this class is the vector of flags and the
  58  * associated methods for reading them.  Any object that can rely
  59  * solely on these flags can process instructions without being
  60  * recompiled for multiple ISAs.
  61  */
  62 class StaticInstBase : public RefCounted
  63 {
  64   protected:
  65
  66     /// Set of boolean static instruction properties.
  67     ///
  68     /// Notes:
  69     /// - The IsInteger and IsFloating flags are based on the class of
  70     /// registers accessed by the instruction.  Although most
  71     /// instructions will have exactly one of these two flags set, it
  72     /// is possible for an instruction to have neither (e.g., direct
  73     /// unconditional branches, memory barriers) or both (e.g., an
  74     /// FP/int conversion).
  75     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  76     /// will be set.  Prefetches are marked as IsLoad, even if they
  77     /// prefetch exclusive copies.
  78     /// - If IsControl is set, then exactly one of IsDirectControl or
  79     /// IsIndirect Control will be set, and exactly one of
  80     /// IsCondControl or IsUncondControl will be set.
  81     /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
  82     /// implemented as flags since in the current model there's no
  83     /// other way for instructions to inject behavior into the
  84     /// pipeline outside of fetch.  Once we go to an exec-in-exec CPU
  85     /// model we should be able to get rid of these flags and
  86     /// implement this behavior via the execute() methods.
  87     ///
  88     enum Flags {
  89         IsNop,          ///< Is a no-op (no effect at all).
  90
  91         IsInteger,      ///< References integer regs.
  92         IsFloating,     ///< References FP regs.
  93
  94         IsMemRef,       ///< References memory (load, store, or prefetch).
  95         IsLoad,         ///< Reads from memory (load or prefetch).
  96         IsStore,        ///< Writes to memory.
  97         IsInstPrefetch, ///< Instruction-cache prefetch.
  98         IsDataPrefetch, ///< Data-cache prefetch.
  99
 100         IsControl,              ///< Control transfer instruction.
 101         IsDirectControl,        ///< PC relative control transfer.
 102         IsIndirectControl,      ///< Register indirect control transfer.
 103         IsCondControl,          ///< Conditional control transfer.
 104         IsUncondControl,        ///< Unconditional control transfer.
 105         IsCall,                 ///< Subroutine call.
 106         IsReturn,               ///< Subroutine return.
 107
 108         IsThreadSync,   ///< Thread synchronization operation.
 109
 110         IsSerializing,  ///< Serializes pipeline: won't until all
 111                         /// older instructions have committed.
 112         IsMemBarrier,   ///< Is a memory barrier
 113         IsWriteBarrier, ///< Is a write barrier
 114
 115         NumFlags
 116     };
 117
 118     /// Flag values for this instruction.
 119     std::bitset<NumFlags> flags;
 120
 121     /// See opClass().
 122     OpClass _opClass;
 123
 124     /// See numSrcRegs().
 125     int8_t _numSrcRegs;
 126
 127     /// See numDestRegs().
 128     int8_t _numDestRegs;
 129
 130     /// The following are used to track physical register usage
 131     /// for machines with separate int & FP reg files.
 132     //@{
 133     int8_t _numFPDestRegs;
 134     int8_t _numIntDestRegs;
 135     //@}
 136
 137     /// Constructor.
 138     /// It's important to initialize everything here to a sane
 139     /// default, since the decoder generally only overrides
 140     /// the fields that are meaningful for the particular
 141     /// instruction.
 142     StaticInstBase(OpClass __opClass)
 143         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 144           _numFPDestRegs(0), _numIntDestRegs(0)
 145     {
 146     }
 147
 148   public:
 149
 150     /// @name Register information.
 151     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 152     /// numDestRegs().  The former two functions are used to track
 153     /// physical register usage for machines with separate int & FP
 154     /// reg files.
 155     //@{
 156     /// Number of source registers.
 157     int8_t numSrcRegs()  const { return _numSrcRegs; }
 158     /// Number of destination registers.
 159     int8_t numDestRegs() const { return _numDestRegs; }
 160     /// Number of floating-point destination regs.
 161     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 162     /// Number of integer destination regs.
 163     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 164     //@}
 165
 166     /// @name Flag accessors.
 167     /// These functions are used to access the values of the various
 168     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 169     /// of the individual flags.
 170     //@{
 171
 172     bool isNop()          const { return flags[IsNop]; }
 173
 174     bool isMemRef()       const { return flags[IsMemRef]; }
 175     bool isLoad()         const { return flags[IsLoad]; }
 176     bool isStore()        const { return flags[IsStore]; }
 177     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 178     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 179
 180     bool isInteger()      const { return flags[IsInteger]; }
 181     bool isFloating()     const { return flags[IsFloating]; }
 182
 183     bool isControl()      const { return flags[IsControl]; }
 184     bool isCall()         const { return flags[IsCall]; }
 185     bool isReturn()       const { return flags[IsReturn]; }
 186     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 187     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 188     bool isCondCtrl()     const { return flags[IsCondControl]; }
 189     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 190
 191     bool isThreadSync()   const { return flags[IsThreadSync]; }
 192     bool isSerializing()  const { return flags[IsSerializing]; }
 193     bool isMemBarrier()   const { return flags[IsMemBarrier]; }
 194     bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
 195     //@}
 196
 197     /// Operation class.  Used to select appropriate function unit in issue.
 198     OpClass opClass()     const { return _opClass; }
 199 };
 200
 201
 202 // forward declaration
 203 template <class ISA>
 204 class StaticInstPtr;
 205
 206 /**
 207  * Generic yet ISA-dependent static instruction class.
 208  *
 209  * This class builds on StaticInstBase, defining fields and interfaces
 210  * that are generic across all ISAs but that differ in details
 211  * according to the specific ISA being used.
 212  */
 213 template <class ISA>
 214 class StaticInst : public StaticInstBase
 215 {
 216   public:
 217
 218     /// Binary machine instruction type.
 219     typedef typename ISA::MachInst MachInst;
 220     /// Memory address type.
 221     typedef typename ISA::Addr     Addr;
 222     /// Logical register index type.
 223     typedef typename ISA::RegIndex RegIndex;
 224
 225     enum {
 226         MaxInstSrcRegs = ISA::MaxInstSrcRegs,   //< Max source regs
 227         MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
 228     };
 229
 230
 231     /// Return logical index (architectural reg num) of i'th destination reg.
 232     /// Only the entries from 0 through numDestRegs()-1 are valid.
 233     RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
 234
 235     /// Return logical index (architectural reg num) of i'th source reg.
 236     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 237     RegIndex srcRegIdx(int i)  const { return _srcRegIdx[i]; }
 238
 239     /// Pointer to a statically allocated "null" instruction object.
 240     /// Used to give eaCompInst() and memAccInst() something to return
 241     /// when called on non-memory instructions.
 242     static StaticInstPtr<ISA> nullStaticInstPtr;
 243
 244     /**
 245      * Memory references only: returns "fake" instruction representing
 246      * the effective address part of the memory operation.  Used to
 247      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 248      * just the EA computation.
 249      */
 250     virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
 251
 252     /**
 253      * Memory references only: returns "fake" instruction representing
 254      * the memory access part of the memory operation.  Used to
 255      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 256      * just the memory access (not the EA computation).
 257      */
 258     virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
 259
 260     /// The binary machine instruction.
 261     const MachInst machInst;
 262
 263   protected:
 264
 265     /// See destRegIdx().
 266     RegIndex _destRegIdx[MaxInstDestRegs];
 267     /// See srcRegIdx().
 268     RegIndex _srcRegIdx[MaxInstSrcRegs];
 269
 270     /**
 271      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 272      * methods.  Also useful to readily identify instructions from
 273      * within the debugger when #cachedDisassembly has not been
 274      * initialized.
 275      */
 276     const char *mnemonic;
 277
 278     /**
 279      * String representation of disassembly (lazily evaluated via
 280      * disassemble()).
 281      */
 282     std::string *cachedDisassembly;
 283
 284     /**
 285      * Internal function to generate disassembly string.
 286      */
 287     virtual std::string generateDisassembly(Addr pc,
 288                                             const SymbolTable *symtab) = 0;
 289
 290     /// Constructor.
 291     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
 292         : StaticInstBase(__opClass),
 293           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 294     {
 295     }
 296
 297   public:
 298
 299     virtual ~StaticInst()
 300     {
 301         if (cachedDisassembly)
 302             delete cachedDisassembly;
 303     }
 304
 305     /**
 306      * Execute this instruction under SimpleCPU model.
 307      */
 308     virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
 309                           Trace::InstRecord *traceData) = 0;
 310
 311     /**
 312      * Execute this instruction under detailed FullCPU model.
 313      */
 314     virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
 315                           Trace::InstRecord *traceData) = 0;
 316
 317     /**
 318      * Return the target address for a PC-relative branch.
 319      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 320      * should be true).
 321      */
 322     virtual Addr branchTarget(Addr branchPC) const
 323     {
 324         panic("StaticInst::branchTarget() called on instruction "
 325               "that is not a PC-relative branch.");
 326     }
 327
 328     /**
 329      * Return the target address for an indirect branch (jump).  The
 330      * register value is read from the supplied execution context, so
 331      * the result is valid only if the execution context is about to
 332      * execute the branch in question.  Invalid if not an indirect
 333      * branch (i.e. isIndirectCtrl() should be true).
 334      */
 335     virtual Addr branchTarget(ExecContext *xc) const
 336     {
 337         panic("StaticInst::branchTarget() called on instruction "
 338               "that is not an indirect branch.");
 339     }
 340
 341     /**
 342      * Return true if the instruction is a control transfer, and if so,
 343      * return the target address as well.
 344      */
 345     bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
 346
 347     /**
 348      * Return string representation of disassembled instruction.
 349      * The default version of this function will call the internal
 350      * virtual generateDisassembly() function to get the string,
 351      * then cache it in #cachedDisassembly.  If the disassembly
 352      * should not be cached, this function should be overridden directly.
 353      */
 354     virtual const std::string &disassemble(Addr pc,
 355                                            const SymbolTable *symtab = 0)
 356     {
 357         if (!cachedDisassembly)
 358             cachedDisassembly =
 359                 new std::string(generateDisassembly(pc, symtab));
 360
 361         return *cachedDisassembly;
 362     }
 363
 364     /// Decoded instruction cache type.
 365     /// For now we're using a generic hash_map; this seems to work
 366     /// pretty well.
 367     typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
 368
 369     /// A cache of decoded instruction objects.
 370     static DecodeCache decodeCache;
 371
 372     /**
 373      * Dump some basic stats on the decode cache hash map.
 374      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 375      */
 376     static void dumpDecodeCacheStats();
 377
 378     /// Decode a machine instruction.
 379     /// @param mach_inst The binary instruction to decode.
 380     /// @retval A pointer to the corresponding StaticInst object.
 381     static
 382     StaticInstPtr<ISA> decode(MachInst mach_inst)
 383     {
 384 #ifdef DECODE_CACHE_HASH_STATS
 385         // Simple stats on decode hash_map.  Turns out the default
 386         // hash function is as good as anything I could come up with.
 387         const int dump_every_n = 10000000;
 388         static int decodes_til_dump = dump_every_n;
 389
 390         if (--decodes_til_dump == 0) {
 391             dumpDecodeCacheStats();
 392             decodes_til_dump = dump_every_n;
 393         }
 394 #endif
 395
 396         typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
 397         if (iter != decodeCache.end()) {
 398             return iter->second;
 399         }
 400
 401         StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
 402         decodeCache[mach_inst] = si;
 403         return si;
 404     }
 405 };
 406
 407 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 408
 409 /// Reference-counted pointer to a StaticInst object.
 410 /// This type should be used instead of "StaticInst<ISA> *" so that
 411 /// StaticInst objects can be properly reference-counted.
 412 template <class ISA>
 413 class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
 414 {
 415   public:
 416     /// Constructor.
 417     StaticInstPtr()
 418         : RefCountingPtr<StaticInst<ISA> >()
 419     {
 420     }
 421
 422     /// Conversion from "StaticInst<ISA> *".
 423     StaticInstPtr(StaticInst<ISA> *p)
 424         : RefCountingPtr<StaticInst<ISA> >(p)
 425     {
 426     }
 427
 428     /// Copy constructor.
 429     StaticInstPtr(const StaticInstPtr &r)
 430         : RefCountingPtr<StaticInst<ISA> >(r)
 431     {
 432     }
 433
 434     /// Construct directly from machine instruction.
 435     /// Calls StaticInst<ISA>::decode().
 436     StaticInstPtr(typename ISA::MachInst mach_inst)
 437         : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
 438     {
 439     }
 440
 441     /// Convert to pointer to StaticInstBase class.
 442     operator const StaticInstBasePtr()
 443     {
 444         return get();
 445     }
 446 };
 447
 448 #endif // __STATIC_INST_HH__