cpu/static_inst.hh

   1 /*
   2  * Copyright (c) 2003 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __STATIC_INST_HH__
  30 #define __STATIC_INST_HH__
  31
  32 #include <bitset>
  33 #include <string>
  34
  35 #include "sim/host.hh"
  36 #include "base/hashmap.hh"
  37 #include "base/refcnt.hh"
  38
  39 #include "cpu/full_cpu/op_class.hh"
  40 #include "targetarch/isa_traits.hh"
  41
  42 // forward declarations
  43 class ExecContext;
  44 class SpecExecContext;
  45 class SimpleCPU;
  46 class FullCPU;
  47 class DynInst;
  48 class SymbolTable;
  49
  50 namespace Trace {
  51     class InstRecord;
  52 }
  53
  54 /**
  55  * Base, ISA-independent static instruction class.
  56  *
  57  * The main component of this class is the vector of flags and the
  58  * associated methods for reading them.  Any object that can rely
  59  * solely on these flags can process instructions without being
  60  * recompiled for multiple ISAs.
  61  */
  62 class StaticInstBase : public RefCounted
  63 {
  64   protected:
  65
  66     /// Set of boolean static instruction properties.
  67     ///
  68     /// Notes:
  69     /// - The IsInteger and IsFloating flags are based on the class of
  70     /// registers accessed by the instruction.  Although most
  71     /// instructions will have exactly one of these two flags set, it
  72     /// is possible for an instruction to have neither (e.g., direct
  73     /// unconditional branches, memory barriers) or both (e.g., an
  74     /// FP/int conversion).
  75     /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
  76     /// will be set.  Prefetches are marked as IsLoad, even if they
  77     /// prefetch exclusive copies.
  78     /// - If IsControl is set, then exactly one of IsDirectControl or
  79     /// IsIndirect Control will be set, and exactly one of
  80     /// IsCondControl or IsUncondControl will be set.
  81     ///
  82     enum Flags {
  83         IsNop,          ///< Is a no-op (no effect at all).
  84
  85         IsInteger,      ///< References integer regs.
  86         IsFloating,     ///< References FP regs.
  87
  88         IsMemRef,       ///< References memory (load, store, or prefetch).
  89         IsLoad,         ///< Reads from memory (load or prefetch).
  90         IsStore,        ///< Writes to memory.
  91         IsInstPrefetch, ///< Instruction-cache prefetch.
  92         IsDataPrefetch, ///< Data-cache prefetch.
  93
  94         IsControl,              ///< Control transfer instruction.
  95         IsDirectControl,        ///< PC relative control transfer.
  96         IsIndirectControl,      ///< Register indirect control transfer.
  97         IsCondControl,          ///< Conditional control transfer.
  98         IsUncondControl,        ///< Unconditional control transfer.
  99         IsCall,                 ///< Subroutine call.
 100         IsReturn,               ///< Subroutine return.
 101
 102         IsThreadSync,           ///< Thread synchronization operation.
 103
 104         NumFlags
 105     };
 106
 107     /// Flag values for this instruction.
 108     std::bitset<NumFlags> flags;
 109
 110     /// See opClass().
 111     OpClass _opClass;
 112
 113     /// See numSrcRegs().
 114     int8_t _numSrcRegs;
 115
 116     /// See numDestRegs().
 117     int8_t _numDestRegs;
 118
 119     /// The following are used to track physical register usage
 120     /// for machines with separate int & FP reg files.
 121     //@{
 122     int8_t _numFPDestRegs;
 123     int8_t _numIntDestRegs;
 124     //@}
 125
 126     /// Constructor.
 127     /// It's important to initialize everything here to a sane
 128     /// default, since the decoder generally only overrides
 129     /// the fields that are meaningful for the particular
 130     /// instruction.
 131     StaticInstBase(OpClass __opClass)
 132         : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
 133           _numFPDestRegs(0), _numIntDestRegs(0)
 134     {
 135     }
 136
 137   public:
 138
 139     /// @name Register information.
 140     /// The sum of numFPDestRegs() and numIntDestRegs() equals
 141     /// numDestRegs().  The former two functions are used to track
 142     /// physical register usage for machines with separate int & FP
 143     /// reg files.
 144     //@{
 145     /// Number of source registers.
 146     int8_t numSrcRegs()  const { return _numSrcRegs; }
 147     /// Number of destination registers.
 148     int8_t numDestRegs() const { return _numDestRegs; }
 149     /// Number of floating-point destination regs.
 150     int8_t numFPDestRegs()  const { return _numFPDestRegs; }
 151     /// Number of integer destination regs.
 152     int8_t numIntDestRegs() const { return _numIntDestRegs; }
 153     //@}
 154
 155     /// @name Flag accessors.
 156     /// These functions are used to access the values of the various
 157     /// instruction property flags.  See StaticInstBase::Flags for descriptions
 158     /// of the individual flags.
 159     //@{
 160
 161     bool isNop()          const { return flags[IsNop]; }
 162
 163     bool isMemRef()       const { return flags[IsMemRef]; }
 164     bool isLoad()         const { return flags[IsLoad]; }
 165     bool isStore()        const { return flags[IsStore]; }
 166     bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
 167     bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
 168
 169     bool isInteger()      const { return flags[IsInteger]; }
 170     bool isFloating()     const { return flags[IsFloating]; }
 171
 172     bool isControl()      const { return flags[IsControl]; }
 173     bool isCall()         const { return flags[IsCall]; }
 174     bool isReturn()       const { return flags[IsReturn]; }
 175     bool isDirectCtrl()   const { return flags[IsDirectControl]; }
 176     bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
 177     bool isCondCtrl()     const { return flags[IsCondControl]; }
 178     bool isUncondCtrl()   const { return flags[IsUncondControl]; }
 179
 180     bool isThreadSync()   const { return flags[IsThreadSync]; }
 181     //@}
 182
 183     /// Operation class.  Used to select appropriate function unit in issue.
 184     OpClass opClass()     const { return _opClass; }
 185 };
 186
 187
 188 // forward declaration
 189 template <class ISA>
 190 class StaticInstPtr;
 191
 192 /**
 193  * Generic yet ISA-dependent static instruction class.
 194  *
 195  * This class builds on StaticInstBase, defining fields and interfaces
 196  * that are generic across all ISAs but that differ in details
 197  * according to the specific ISA being used.
 198  */
 199 template <class ISA>
 200 class StaticInst : public StaticInstBase
 201 {
 202   public:
 203
 204     /// Binary machine instruction type.
 205     typedef typename ISA::MachInst MachInst;
 206     /// Memory address type.
 207     typedef typename ISA::Addr     Addr;
 208     /// Logical register index type.
 209     typedef typename ISA::RegIndex RegIndex;
 210
 211     enum {
 212         MaxInstSrcRegs = ISA::MaxInstSrcRegs,   //< Max source regs
 213         MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
 214     };
 215
 216
 217     /// Return logical index (architectural reg num) of i'th destination reg.
 218     /// Only the entries from 0 through numDestRegs()-1 are valid.
 219     RegIndex destRegIdx(int i)  { return _destRegIdx[i]; }
 220
 221     /// Return logical index (architectural reg num) of i'th source reg.
 222     /// Only the entries from 0 through numSrcRegs()-1 are valid.
 223     RegIndex srcRegIdx(int i)   { return _srcRegIdx[i]; }
 224
 225     /// Pointer to a statically allocated "null" instruction object.
 226     /// Used to give eaCompInst() and memAccInst() something to return
 227     /// when called on non-memory instructions.
 228     static StaticInstPtr<ISA> nullStaticInstPtr;
 229
 230     /**
 231      * Memory references only: returns "fake" instruction representing
 232      * the effective address part of the memory operation.  Used to
 233      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 234      * just the EA computation.
 235      */
 236     virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
 237
 238     /**
 239      * Memory references only: returns "fake" instruction representing
 240      * the memory access part of the memory operation.  Used to
 241      * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
 242      * just the memory access (not the EA computation).
 243      */
 244     virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
 245
 246     /// The binary machine instruction.
 247     const MachInst machInst;
 248
 249   protected:
 250
 251     /// See destRegIdx().
 252     RegIndex _destRegIdx[MaxInstDestRegs];
 253     /// See srcRegIdx().
 254     RegIndex _srcRegIdx[MaxInstSrcRegs];
 255
 256     /**
 257      * Base mnemonic (e.g., "add").  Used by generateDisassembly()
 258      * methods.  Also useful to readily identify instructions from
 259      * within the debugger when #cachedDisassembly has not been
 260      * initialized.
 261      */
 262     const char *mnemonic;
 263
 264     /**
 265      * String representation of disassembly (lazily evaluated via
 266      * disassemble()).
 267      */
 268     std::string *cachedDisassembly;
 269
 270     /**
 271      * Internal function to generate disassembly string.
 272      */
 273     virtual std::string generateDisassembly(Addr pc,
 274                                             const SymbolTable *symtab) = 0;
 275
 276     /// Constructor.
 277     StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
 278         : StaticInstBase(__opClass),
 279           machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
 280     {
 281     }
 282
 283   public:
 284
 285     virtual ~StaticInst()
 286     {
 287         if (cachedDisassembly)
 288             delete cachedDisassembly;
 289     }
 290
 291     /**
 292      * Execute this instruction under SimpleCPU model.
 293      */
 294     virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
 295                           Trace::InstRecord *traceData) = 0;
 296
 297     /**
 298      * Execute this instruction under detailed FullCPU model.
 299      */
 300     virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
 301                           Trace::InstRecord *traceData) = 0;
 302
 303     /**
 304      * Return the target address for a PC-relative branch.
 305      * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
 306      * should be true).
 307      */
 308     virtual Addr branchTarget(Addr branchPC)
 309     {
 310         panic("StaticInst::branchTarget() called on instruction "
 311               "that is not a PC-relative branch.");
 312     }
 313
 314     /**
 315      * Return the target address for an indirect branch (jump).
 316      * The register value is read from the supplied execution context.
 317      * Invalid if not an indirect branch (i.e. isIndirectCtrl()
 318      * should be true).
 319      */
 320     virtual Addr branchTarget(ExecContext *xc)
 321     {
 322         panic("StaticInst::branchTarget() called on instruction "
 323               "that is not an indirect branch.");
 324     }
 325
 326     /**
 327      * Return true if the instruction is a control transfer, and if so,
 328      * return the target address as well.
 329      */
 330     bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
 331
 332     /**
 333      * Return string representation of disassembled instruction.
 334      * The default version of this function will call the internal
 335      * virtual generateDisassembly() function to get the string,
 336      * then cache it in #cachedDisassembly.  If the disassembly
 337      * should not be cached, this function should be overridden directly.
 338      */
 339     virtual const std::string &disassemble(Addr pc,
 340                                            const SymbolTable *symtab = 0)
 341     {
 342         if (!cachedDisassembly)
 343             cachedDisassembly =
 344                 new std::string(generateDisassembly(pc, symtab));
 345
 346         return *cachedDisassembly;
 347     }
 348
 349     /// Decoded instruction cache type.
 350     /// For now we're using a generic hash_map; this seems to work
 351     /// pretty well.
 352     typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
 353
 354     /// A cache of decoded instruction objects.
 355     static DecodeCache decodeCache;
 356
 357     /**
 358      * Dump some basic stats on the decode cache hash map.
 359      * Only gets called if DECODE_CACHE_HASH_STATS is defined.
 360      */
 361     static void dumpDecodeCacheStats();
 362
 363     /// Decode a machine instruction.
 364     /// @param mach_inst The binary instruction to decode.
 365     /// @retval A pointer to the corresponding StaticInst object.
 366     static
 367     StaticInstPtr<ISA> decode(MachInst mach_inst)
 368     {
 369 #ifdef DECODE_CACHE_HASH_STATS
 370         // Simple stats on decode hash_map.  Turns out the default
 371         // hash function is as good as anything I could come up with.
 372         const int dump_every_n = 10000000;
 373         static int decodes_til_dump = dump_every_n;
 374
 375         if (--decodes_til_dump == 0) {
 376             dumpDecodeCacheStats();
 377             decodes_til_dump = dump_every_n;
 378         }
 379 #endif
 380
 381         typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
 382         if (iter != decodeCache.end()) {
 383             return iter->second;
 384         }
 385
 386         StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
 387         decodeCache[mach_inst] = si;
 388         return si;
 389     }
 390 };
 391
 392 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
 393
 394 /// Reference-counted pointer to a StaticInst object.
 395 /// This type should be used instead of "StaticInst<ISA> *" so that
 396 /// StaticInst objects can be properly reference-counted.
 397 template <class ISA>
 398 class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
 399 {
 400   public:
 401     /// Constructor.
 402     StaticInstPtr()
 403         : RefCountingPtr<StaticInst<ISA> >()
 404     {
 405     }
 406
 407     /// Conversion from "StaticInst<ISA> *".
 408     StaticInstPtr(StaticInst<ISA> *p)
 409         : RefCountingPtr<StaticInst<ISA> >(p)
 410     {
 411     }
 412
 413     /// Copy constructor.
 414     StaticInstPtr(const StaticInstPtr &r)
 415         : RefCountingPtr<StaticInst<ISA> >(r)
 416     {
 417     }
 418
 419     /// Construct directly from machine instruction.
 420     /// Calls StaticInst<ISA>::decode().
 421     StaticInstPtr(typename ISA::MachInst mach_inst)
 422         : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
 423     {
 424     }
 425
 426     /// Convert to pointer to StaticInstBase class.
 427     operator const StaticInstBasePtr()
 428     {
 429         return get();
 430     }
 431 };
 432
 433 #endif // __STATIC_INST_HH__