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29 #ifndef __STATIC_INST_HH__
30 #define __STATIC_INST_HH__
35 #include "sim/host.hh"
36 #include "base/hashmap.hh"
37 #include "base/refcnt.hh"
39 #include "cpu/full_cpu/op_class.hh"
40 #include "targetarch/isa_traits.hh"
42 // forward declarations
55 * Base, ISA-independent static instruction class.
57 * The main component of this class is the vector of flags and the
58 * associated methods for reading them. Any object that can rely
59 * solely on these flags can process instructions without being
60 * recompiled for multiple ISAs.
62 class StaticInstBase : public RefCounted
66 /// Set of boolean static instruction properties.
69 /// - The IsInteger and IsFloating flags are based on the class of
70 /// registers accessed by the instruction. Although most
71 /// instructions will have exactly one of these two flags set, it
72 /// is possible for an instruction to have neither (e.g., direct
73 /// unconditional branches, memory barriers) or both (e.g., an
74 /// FP/int conversion).
75 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
77 /// - If IsControl is set, then exactly one of IsDirectControl or
78 /// IsIndirect Control will be set, and exactly one of
79 /// IsCondControl or IsUncondControl will be set.
80 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
81 /// implemented as flags since in the current model there's no
82 /// other way for instructions to inject behavior into the
83 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
84 /// model we should be able to get rid of these flags and
85 /// implement this behavior via the execute() methods.
88 IsNop, ///< Is a no-op (no effect at all).
90 IsInteger, ///< References integer regs.
91 IsFloating, ///< References FP regs.
93 IsMemRef, ///< References memory (load, store, or prefetch).
94 IsLoad, ///< Reads from memory (load or prefetch).
95 IsStore, ///< Writes to memory.
96 IsInstPrefetch, ///< Instruction-cache prefetch.
97 IsDataPrefetch, ///< Data-cache prefetch.
98 IsCopy, ///< Fast Cache block copy
100 IsControl, ///< Control transfer instruction.
101 IsDirectControl, ///< PC relative control transfer.
102 IsIndirectControl, ///< Register indirect control transfer.
103 IsCondControl, ///< Conditional control transfer.
104 IsUncondControl, ///< Unconditional control transfer.
105 IsCall, ///< Subroutine call.
106 IsReturn, ///< Subroutine return.
108 IsThreadSync, ///< Thread synchronization operation.
110 IsSerializing, ///< Serializes pipeline: won't execute until all
111 /// older instructions have committed.
112 IsMemBarrier, ///< Is a memory barrier
113 IsWriteBarrier, ///< Is a write barrier
115 IsNonSpeculative, ///< Should not be executed speculatively
120 /// Flag values for this instruction.
121 std::bitset<NumFlags> flags;
126 /// See numSrcRegs().
129 /// See numDestRegs().
132 /// The following are used to track physical register usage
133 /// for machines with separate int & FP reg files.
135 int8_t _numFPDestRegs;
136 int8_t _numIntDestRegs;
140 /// It's important to initialize everything here to a sane
141 /// default, since the decoder generally only overrides
142 /// the fields that are meaningful for the particular
144 StaticInstBase(OpClass __opClass)
145 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
146 _numFPDestRegs(0), _numIntDestRegs(0)
152 /// @name Register information.
153 /// The sum of numFPDestRegs() and numIntDestRegs() equals
154 /// numDestRegs(). The former two functions are used to track
155 /// physical register usage for machines with separate int & FP
158 /// Number of source registers.
159 int8_t numSrcRegs() const { return _numSrcRegs; }
160 /// Number of destination registers.
161 int8_t numDestRegs() const { return _numDestRegs; }
162 /// Number of floating-point destination regs.
163 int8_t numFPDestRegs() const { return _numFPDestRegs; }
164 /// Number of integer destination regs.
165 int8_t numIntDestRegs() const { return _numIntDestRegs; }
168 /// @name Flag accessors.
169 /// These functions are used to access the values of the various
170 /// instruction property flags. See StaticInstBase::Flags for descriptions
171 /// of the individual flags.
174 bool isNop() const { return flags[IsNop]; }
176 bool isMemRef() const { return flags[IsMemRef]; }
177 bool isLoad() const { return flags[IsLoad]; }
178 bool isStore() const { return flags[IsStore]; }
179 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
180 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
181 bool isCopy() const { return flags[IsCopy];}
183 bool isInteger() const { return flags[IsInteger]; }
184 bool isFloating() const { return flags[IsFloating]; }
186 bool isControl() const { return flags[IsControl]; }
187 bool isCall() const { return flags[IsCall]; }
188 bool isReturn() const { return flags[IsReturn]; }
189 bool isDirectCtrl() const { return flags[IsDirectControl]; }
190 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
191 bool isCondCtrl() const { return flags[IsCondControl]; }
192 bool isUncondCtrl() const { return flags[IsUncondControl]; }
194 bool isThreadSync() const { return flags[IsThreadSync]; }
195 bool isSerializing() const { return flags[IsSerializing]; }
196 bool isMemBarrier() const { return flags[IsMemBarrier]; }
197 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
198 bool isNonSpeculative() const { return flags[IsNonSpeculative]; }
201 /// Operation class. Used to select appropriate function unit in issue.
202 OpClass opClass() const { return _opClass; }
206 // forward declaration
211 * Generic yet ISA-dependent static instruction class.
213 * This class builds on StaticInstBase, defining fields and interfaces
214 * that are generic across all ISAs but that differ in details
215 * according to the specific ISA being used.
218 class StaticInst : public StaticInstBase
222 /// Binary machine instruction type.
223 typedef typename ISA::MachInst MachInst;
224 /// Memory address type.
225 typedef typename ISA::Addr Addr;
226 /// Logical register index type.
227 typedef typename ISA::RegIndex RegIndex;
230 MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
231 MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
235 /// Return logical index (architectural reg num) of i'th destination reg.
236 /// Only the entries from 0 through numDestRegs()-1 are valid.
237 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
239 /// Return logical index (architectural reg num) of i'th source reg.
240 /// Only the entries from 0 through numSrcRegs()-1 are valid.
241 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
243 /// Pointer to a statically allocated "null" instruction object.
244 /// Used to give eaCompInst() and memAccInst() something to return
245 /// when called on non-memory instructions.
246 static StaticInstPtr<ISA> nullStaticInstPtr;
249 * Memory references only: returns "fake" instruction representing
250 * the effective address part of the memory operation. Used to
251 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
252 * just the EA computation.
255 StaticInstPtr<ISA> &eaCompInst() const { return nullStaticInstPtr; }
258 * Memory references only: returns "fake" instruction representing
259 * the memory access part of the memory operation. Used to
260 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
261 * just the memory access (not the EA computation).
264 StaticInstPtr<ISA> &memAccInst() const { return nullStaticInstPtr; }
266 /// The binary machine instruction.
267 const MachInst machInst;
271 /// See destRegIdx().
272 RegIndex _destRegIdx[MaxInstDestRegs];
274 RegIndex _srcRegIdx[MaxInstSrcRegs];
277 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
278 * methods. Also useful to readily identify instructions from
279 * within the debugger when #cachedDisassembly has not been
282 const char *mnemonic;
285 * String representation of disassembly (lazily evaluated via
288 std::string *cachedDisassembly;
291 * Internal function to generate disassembly string.
293 virtual std::string generateDisassembly(Addr pc,
294 const SymbolTable *symtab) = 0;
297 StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
298 : StaticInstBase(__opClass),
299 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
305 virtual ~StaticInst()
307 if (cachedDisassembly)
308 delete cachedDisassembly;
311 #include "static_inst_impl.hh"
314 * Return the target address for a PC-relative branch.
315 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
318 virtual Addr branchTarget(Addr branchPC) const
320 panic("StaticInst::branchTarget() called on instruction "
321 "that is not a PC-relative branch.");
325 * Return the target address for an indirect branch (jump). The
326 * register value is read from the supplied execution context, so
327 * the result is valid only if the execution context is about to
328 * execute the branch in question. Invalid if not an indirect
329 * branch (i.e. isIndirectCtrl() should be true).
331 virtual Addr branchTarget(ExecContext *xc) const
333 panic("StaticInst::branchTarget() called on instruction "
334 "that is not an indirect branch.");
338 * Return true if the instruction is a control transfer, and if so,
339 * return the target address as well.
341 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
344 * Return string representation of disassembled instruction.
345 * The default version of this function will call the internal
346 * virtual generateDisassembly() function to get the string,
347 * then cache it in #cachedDisassembly. If the disassembly
348 * should not be cached, this function should be overridden directly.
350 virtual const std::string &disassemble(Addr pc,
351 const SymbolTable *symtab = 0)
353 if (!cachedDisassembly)
355 new std::string(generateDisassembly(pc, symtab));
357 return *cachedDisassembly;
360 /// Decoded instruction cache type.
361 /// For now we're using a generic hash_map; this seems to work
363 typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
365 /// A cache of decoded instruction objects.
366 static DecodeCache decodeCache;
369 * Dump some basic stats on the decode cache hash map.
370 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
372 static void dumpDecodeCacheStats();
374 /// Decode a machine instruction.
375 /// @param mach_inst The binary instruction to decode.
376 /// @retval A pointer to the corresponding StaticInst object.
378 StaticInstPtr<ISA> decode(MachInst mach_inst)
380 #ifdef DECODE_CACHE_HASH_STATS
381 // Simple stats on decode hash_map. Turns out the default
382 // hash function is as good as anything I could come up with.
383 const int dump_every_n = 10000000;
384 static int decodes_til_dump = dump_every_n;
386 if (--decodes_til_dump == 0) {
387 dumpDecodeCacheStats();
388 decodes_til_dump = dump_every_n;
392 typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
393 if (iter != decodeCache.end()) {
397 StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
398 decodeCache[mach_inst] = si;
403 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
405 /// Reference-counted pointer to a StaticInst object.
406 /// This type should be used instead of "StaticInst<ISA> *" so that
407 /// StaticInst objects can be properly reference-counted.
409 class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
414 : RefCountingPtr<StaticInst<ISA> >()
418 /// Conversion from "StaticInst<ISA> *".
419 StaticInstPtr(StaticInst<ISA> *p)
420 : RefCountingPtr<StaticInst<ISA> >(p)
424 /// Copy constructor.
425 StaticInstPtr(const StaticInstPtr &r)
426 : RefCountingPtr<StaticInst<ISA> >(r)
430 /// Construct directly from machine instruction.
431 /// Calls StaticInst<ISA>::decode().
432 StaticInstPtr(typename ISA::MachInst mach_inst)
433 : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
437 /// Convert to pointer to StaticInstBase class.
438 operator const StaticInstBasePtr()
444 #endif // __STATIC_INST_HH__