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29 #ifndef __STATIC_INST_HH__
30 #define __STATIC_INST_HH__
35 #include "sim/host.hh"
36 #include "base/hashmap.hh"
37 #include "base/refcnt.hh"
39 #include "cpu/full_cpu/op_class.hh"
40 #include "targetarch/isa_traits.hh"
42 // forward declarations
44 class SpecExecContext;
55 * Base, ISA-independent static instruction class.
57 * The main component of this class is the vector of flags and the
58 * associated methods for reading them. Any object that can rely
59 * solely on these flags can process instructions without being
60 * recompiled for multiple ISAs.
62 class StaticInstBase : public RefCounted
66 /// Set of boolean static instruction properties.
69 /// - The IsInteger and IsFloating flags are based on the class of
70 /// registers accessed by the instruction. Although most
71 /// instructions will have exactly one of these two flags set, it
72 /// is possible for an instruction to have neither (e.g., direct
73 /// unconditional branches, memory barriers) or both (e.g., an
74 /// FP/int conversion).
75 /// - If IsMemRef is set, then exactly one of IsLoad or IsStore
76 /// will be set. Prefetches are marked as IsLoad, even if they
77 /// prefetch exclusive copies.
78 /// - If IsControl is set, then exactly one of IsDirectControl or
79 /// IsIndirect Control will be set, and exactly one of
80 /// IsCondControl or IsUncondControl will be set.
81 /// - IsSerializing, IsMemBarrier, and IsWriteBarrier are
82 /// implemented as flags since in the current model there's no
83 /// other way for instructions to inject behavior into the
84 /// pipeline outside of fetch. Once we go to an exec-in-exec CPU
85 /// model we should be able to get rid of these flags and
86 /// implement this behavior via the execute() methods.
89 IsNop, ///< Is a no-op (no effect at all).
91 IsInteger, ///< References integer regs.
92 IsFloating, ///< References FP regs.
94 IsMemRef, ///< References memory (load, store, or prefetch).
95 IsLoad, ///< Reads from memory (load or prefetch).
96 IsStore, ///< Writes to memory.
97 IsInstPrefetch, ///< Instruction-cache prefetch.
98 IsDataPrefetch, ///< Data-cache prefetch.
99 IsCopy, ///< Fast Cache block copy
101 IsControl, ///< Control transfer instruction.
102 IsDirectControl, ///< PC relative control transfer.
103 IsIndirectControl, ///< Register indirect control transfer.
104 IsCondControl, ///< Conditional control transfer.
105 IsUncondControl, ///< Unconditional control transfer.
106 IsCall, ///< Subroutine call.
107 IsReturn, ///< Subroutine return.
109 IsThreadSync, ///< Thread synchronization operation.
111 IsSerializing, ///< Serializes pipeline: won't until all
112 /// older instructions have committed.
113 IsMemBarrier, ///< Is a memory barrier
114 IsWriteBarrier, ///< Is a write barrier
119 /// Flag values for this instruction.
120 std::bitset<NumFlags> flags;
125 /// See numSrcRegs().
128 /// See numDestRegs().
131 /// The following are used to track physical register usage
132 /// for machines with separate int & FP reg files.
134 int8_t _numFPDestRegs;
135 int8_t _numIntDestRegs;
139 /// It's important to initialize everything here to a sane
140 /// default, since the decoder generally only overrides
141 /// the fields that are meaningful for the particular
143 StaticInstBase(OpClass __opClass)
144 : _opClass(__opClass), _numSrcRegs(0), _numDestRegs(0),
145 _numFPDestRegs(0), _numIntDestRegs(0)
151 /// @name Register information.
152 /// The sum of numFPDestRegs() and numIntDestRegs() equals
153 /// numDestRegs(). The former two functions are used to track
154 /// physical register usage for machines with separate int & FP
157 /// Number of source registers.
158 int8_t numSrcRegs() const { return _numSrcRegs; }
159 /// Number of destination registers.
160 int8_t numDestRegs() const { return _numDestRegs; }
161 /// Number of floating-point destination regs.
162 int8_t numFPDestRegs() const { return _numFPDestRegs; }
163 /// Number of integer destination regs.
164 int8_t numIntDestRegs() const { return _numIntDestRegs; }
167 /// @name Flag accessors.
168 /// These functions are used to access the values of the various
169 /// instruction property flags. See StaticInstBase::Flags for descriptions
170 /// of the individual flags.
173 bool isNop() const { return flags[IsNop]; }
175 bool isMemRef() const { return flags[IsMemRef]; }
176 bool isLoad() const { return flags[IsLoad]; }
177 bool isStore() const { return flags[IsStore]; }
178 bool isInstPrefetch() const { return flags[IsInstPrefetch]; }
179 bool isDataPrefetch() const { return flags[IsDataPrefetch]; }
180 bool isCopy() const { return flags[IsCopy];}
182 bool isInteger() const { return flags[IsInteger]; }
183 bool isFloating() const { return flags[IsFloating]; }
185 bool isControl() const { return flags[IsControl]; }
186 bool isCall() const { return flags[IsCall]; }
187 bool isReturn() const { return flags[IsReturn]; }
188 bool isDirectCtrl() const { return flags[IsDirectControl]; }
189 bool isIndirectCtrl() const { return flags[IsIndirectControl]; }
190 bool isCondCtrl() const { return flags[IsCondControl]; }
191 bool isUncondCtrl() const { return flags[IsUncondControl]; }
193 bool isThreadSync() const { return flags[IsThreadSync]; }
194 bool isSerializing() const { return flags[IsSerializing]; }
195 bool isMemBarrier() const { return flags[IsMemBarrier]; }
196 bool isWriteBarrier() const { return flags[IsWriteBarrier]; }
199 /// Operation class. Used to select appropriate function unit in issue.
200 OpClass opClass() const { return _opClass; }
204 // forward declaration
209 * Generic yet ISA-dependent static instruction class.
211 * This class builds on StaticInstBase, defining fields and interfaces
212 * that are generic across all ISAs but that differ in details
213 * according to the specific ISA being used.
216 class StaticInst : public StaticInstBase
220 /// Binary machine instruction type.
221 typedef typename ISA::MachInst MachInst;
222 /// Memory address type.
223 typedef typename ISA::Addr Addr;
224 /// Logical register index type.
225 typedef typename ISA::RegIndex RegIndex;
228 MaxInstSrcRegs = ISA::MaxInstSrcRegs, //< Max source regs
229 MaxInstDestRegs = ISA::MaxInstDestRegs, //< Max dest regs
233 /// Return logical index (architectural reg num) of i'th destination reg.
234 /// Only the entries from 0 through numDestRegs()-1 are valid.
235 RegIndex destRegIdx(int i) const { return _destRegIdx[i]; }
237 /// Return logical index (architectural reg num) of i'th source reg.
238 /// Only the entries from 0 through numSrcRegs()-1 are valid.
239 RegIndex srcRegIdx(int i) const { return _srcRegIdx[i]; }
241 /// Pointer to a statically allocated "null" instruction object.
242 /// Used to give eaCompInst() and memAccInst() something to return
243 /// when called on non-memory instructions.
244 static StaticInstPtr<ISA> nullStaticInstPtr;
247 * Memory references only: returns "fake" instruction representing
248 * the effective address part of the memory operation. Used to
249 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
250 * just the EA computation.
252 virtual StaticInstPtr<ISA> eaCompInst() { return nullStaticInstPtr; }
255 * Memory references only: returns "fake" instruction representing
256 * the memory access part of the memory operation. Used to
257 * obtain the dependence info (numSrcRegs and srcRegIdx[]) for
258 * just the memory access (not the EA computation).
260 virtual StaticInstPtr<ISA> memAccInst() { return nullStaticInstPtr; }
262 /// The binary machine instruction.
263 const MachInst machInst;
267 /// See destRegIdx().
268 RegIndex _destRegIdx[MaxInstDestRegs];
270 RegIndex _srcRegIdx[MaxInstSrcRegs];
273 * Base mnemonic (e.g., "add"). Used by generateDisassembly()
274 * methods. Also useful to readily identify instructions from
275 * within the debugger when #cachedDisassembly has not been
278 const char *mnemonic;
281 * String representation of disassembly (lazily evaluated via
284 std::string *cachedDisassembly;
287 * Internal function to generate disassembly string.
289 virtual std::string generateDisassembly(Addr pc,
290 const SymbolTable *symtab) = 0;
293 StaticInst(const char *_mnemonic, MachInst _machInst, OpClass __opClass)
294 : StaticInstBase(__opClass),
295 machInst(_machInst), mnemonic(_mnemonic), cachedDisassembly(0)
301 virtual ~StaticInst()
303 if (cachedDisassembly)
304 delete cachedDisassembly;
308 * Execute this instruction under SimpleCPU model.
310 virtual Fault execute(SimpleCPU *cpu, ExecContext *xc,
311 Trace::InstRecord *traceData) = 0;
314 * Execute this instruction under detailed FullCPU model.
316 virtual Fault execute(FullCPU *cpu, SpecExecContext *xc, DynInst *dynInst,
317 Trace::InstRecord *traceData) = 0;
320 * Return the target address for a PC-relative branch.
321 * Invalid if not a PC-relative branch (i.e. isDirectCtrl()
324 virtual Addr branchTarget(Addr branchPC) const
326 panic("StaticInst::branchTarget() called on instruction "
327 "that is not a PC-relative branch.");
331 * Return the target address for an indirect branch (jump). The
332 * register value is read from the supplied execution context, so
333 * the result is valid only if the execution context is about to
334 * execute the branch in question. Invalid if not an indirect
335 * branch (i.e. isIndirectCtrl() should be true).
337 virtual Addr branchTarget(ExecContext *xc) const
339 panic("StaticInst::branchTarget() called on instruction "
340 "that is not an indirect branch.");
344 * Return true if the instruction is a control transfer, and if so,
345 * return the target address as well.
347 bool hasBranchTarget(Addr pc, ExecContext *xc, Addr &tgt);
350 * Return string representation of disassembled instruction.
351 * The default version of this function will call the internal
352 * virtual generateDisassembly() function to get the string,
353 * then cache it in #cachedDisassembly. If the disassembly
354 * should not be cached, this function should be overridden directly.
356 virtual const std::string &disassemble(Addr pc,
357 const SymbolTable *symtab = 0)
359 if (!cachedDisassembly)
361 new std::string(generateDisassembly(pc, symtab));
363 return *cachedDisassembly;
366 /// Decoded instruction cache type.
367 /// For now we're using a generic hash_map; this seems to work
369 typedef m5::hash_map<MachInst, StaticInstPtr<ISA> > DecodeCache;
371 /// A cache of decoded instruction objects.
372 static DecodeCache decodeCache;
375 * Dump some basic stats on the decode cache hash map.
376 * Only gets called if DECODE_CACHE_HASH_STATS is defined.
378 static void dumpDecodeCacheStats();
380 /// Decode a machine instruction.
381 /// @param mach_inst The binary instruction to decode.
382 /// @retval A pointer to the corresponding StaticInst object.
384 StaticInstPtr<ISA> decode(MachInst mach_inst)
386 #ifdef DECODE_CACHE_HASH_STATS
387 // Simple stats on decode hash_map. Turns out the default
388 // hash function is as good as anything I could come up with.
389 const int dump_every_n = 10000000;
390 static int decodes_til_dump = dump_every_n;
392 if (--decodes_til_dump == 0) {
393 dumpDecodeCacheStats();
394 decodes_til_dump = dump_every_n;
398 typename DecodeCache::iterator iter = decodeCache.find(mach_inst);
399 if (iter != decodeCache.end()) {
403 StaticInstPtr<ISA> si = ISA::decodeInst(mach_inst);
404 decodeCache[mach_inst] = si;
409 typedef RefCountingPtr<StaticInstBase> StaticInstBasePtr;
411 /// Reference-counted pointer to a StaticInst object.
412 /// This type should be used instead of "StaticInst<ISA> *" so that
413 /// StaticInst objects can be properly reference-counted.
415 class StaticInstPtr : public RefCountingPtr<StaticInst<ISA> >
420 : RefCountingPtr<StaticInst<ISA> >()
424 /// Conversion from "StaticInst<ISA> *".
425 StaticInstPtr(StaticInst<ISA> *p)
426 : RefCountingPtr<StaticInst<ISA> >(p)
430 /// Copy constructor.
431 StaticInstPtr(const StaticInstPtr &r)
432 : RefCountingPtr<StaticInst<ISA> >(r)
436 /// Construct directly from machine instruction.
437 /// Calls StaticInst<ISA>::decode().
438 StaticInstPtr(typename ISA::MachInst mach_inst)
439 : RefCountingPtr<StaticInst<ISA> >(StaticInst<ISA>::decode(mach_inst))
443 /// Convert to pointer to StaticInstBase class.
444 operator const StaticInstBasePtr()
450 #endif // __STATIC_INST_HH__