Merge ktlim@zizzer.eecs.umich.edu:/bk/m5
[gem5.git] / cpu / trace / opt_cpu.hh
1 /*
2 * Copyright (c) 2004 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 */
28
29 /**
30 * @file
31 * Declaration of a memory trace CPU object for optimal caches. Uses a memory
32 * trace to access a fully associative cache with optimal replacement.
33 */
34
35 #ifndef __CPU_TRACE_OPT_CPU_HH__
36 #define __CPU_TRACE_OPT_CPU_HH__
37
38 #include <vector>
39
40 #include "mem/mem_req.hh" // for MemReqPtr
41 #include "sim/eventq.hh" // for Event
42 #include "sim/sim_object.hh"
43
44 // Forward Declaration
45 class MemTraceReader;
46
47 /**
48 * A CPU object to simulate a fully-associative cache with optimal replacement.
49 */
50 class OptCPU : public SimObject
51 {
52 private:
53 typedef int RefIndex;
54
55 typedef std::vector<RefIndex> L3Table;
56 typedef std::vector<L3Table> L2Table;
57 typedef std::vector<L2Table> L1Table;
58
59 /**
60 * Event to call OptCPU::tick
61 */
62 class TickEvent : public Event
63 {
64 private:
65 /** The associated CPU */
66 OptCPU *cpu;
67
68 public:
69 /**
70 * Construct this event;
71 */
72 TickEvent(OptCPU *c);
73
74 /**
75 * Call the tick function.
76 */
77 void process();
78
79 /**
80 * Return a string description of this event.
81 */
82 const char *description();
83 };
84
85 TickEvent tickEvent;
86
87 class RefInfo
88 {
89 public:
90 RefIndex nextRefTime;
91 Addr addr;
92 };
93
94 /** Reference Information, per set. */
95 std::vector<std::vector<RefInfo> > refInfo;
96
97 /** Lookup table to track blocks in the cache heap */
98 L1Table lookupTable;
99
100 /**
101 * Return the correct value in the lookup table.
102 */
103 RefIndex lookupValue(Addr addr)
104 {
105 int l1_index = (addr >> 32) & 0x0f;
106 int l2_index = (addr >> 16) & 0xffff;
107 int l3_index = addr & 0xffff;
108 assert(l1_index == addr >> 32);
109 return lookupTable[l1_index][l2_index][l3_index];
110 }
111
112 /**
113 * Set the value in the lookup table.
114 */
115 void setValue(Addr addr, RefIndex index)
116 {
117 int l1_index = (addr >> 32) & 0x0f;
118 int l2_index = (addr >> 16) & 0xffff;
119 int l3_index = addr & 0xffff;
120 assert(l1_index == addr >> 32);
121 lookupTable[l1_index][l2_index][l3_index]=index;
122 }
123
124 /**
125 * Initialize the lookup table to the given value.
126 */
127 void initTable(Addr addr, RefIndex index);
128
129 void heapSwap(int set, int a, int b) {
130 RefIndex tmp = cacheHeap[a];
131 cacheHeap[a] = cacheHeap[b];
132 cacheHeap[b] = tmp;
133
134 setValue(refInfo[set][cacheHeap[a]].addr, a);
135 setValue(refInfo[set][cacheHeap[b]].addr, b);
136 }
137
138 int heapLeft(int index) { return index + index + 1; }
139 int heapRight(int index) { return index + index + 2; }
140 int heapParent(int index) { return (index - 1) >> 1; }
141
142 RefIndex heapRank(int set, int index) {
143 return refInfo[set][cacheHeap[index]].nextRefTime;
144 }
145
146 void heapify(int set, int start){
147 int left = heapLeft(start);
148 int right = heapRight(start);
149 int max = start;
150 if (left < assoc && heapRank(set, left) > heapRank(set, start)) {
151 max = left;
152 }
153 if (right < assoc && heapRank(set, right) > heapRank(set, max)) {
154 max = right;
155 }
156
157 if (max != start) {
158 heapSwap(set, start, max);
159 heapify(set, max);
160 }
161 }
162
163 void verifyHeap(int set, int start) {
164 int left = heapLeft(start);
165 int right = heapRight(start);
166
167 if (left < assoc) {
168 assert(heapRank(set, start) >= heapRank(set, left));
169 verifyHeap(set, left);
170 }
171 if (right < assoc) {
172 assert(heapRank(set, start) >= heapRank(set, right));
173 verifyHeap(set, right);
174 }
175 }
176
177 void processRankIncrease(int set, int start) {
178 int parent = heapParent(start);
179 while (start > 0 && heapRank(set,parent) < heapRank(set,start)) {
180 heapSwap(set, parent, start);
181 start = parent;
182 parent = heapParent(start);
183 }
184 }
185
186 void processSet(int set);
187
188 static const RefIndex InfiniteRef = 0x7fffffff;
189
190 /** Memory reference trace. */
191 MemTraceReader *trace;
192
193 /** Cache heap for replacement. */
194 std::vector<RefIndex> cacheHeap;
195
196 /** The number of blocks in the cache. */
197 const int numBlks;
198
199 const int assoc;
200 const int numSets;
201 const int setMask;
202
203
204 int misses;
205 int hits;
206
207 public:
208 /**
209 * Construct a OptCPU object.
210 */
211 OptCPU(const std::string &name,
212 MemTraceReader *_trace,
213 int block_size,
214 int cache_size,
215 int assoc);
216
217 /**
218 * Perform the optimal replacement simulation.
219 */
220 void tick();
221 };
222
223 #endif // __CPU_TRACE_OPT_CPU_HH__