cpu/trace/trace_cpu.cc

   1 /*
   2  * Copyright (c) 2004 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 /**
  30  * @file
  31  * Declaration of a memory trace CPU object. Uses a memory trace to drive the
  32  * provided memory hierarchy.
  33  */
  34
  35 #include <algorithm> // For min
  36
  37 #include "cpu/trace/trace_cpu.hh"
  38 #include "cpu/trace/reader/mem_trace_reader.hh"
  39 #include "mem/base_mem.hh" // For PARAM constructor
  40 #include "mem/mem_interface.hh"
  41 #include "sim/builder.hh"
  42 #include "sim/sim_events.hh"
  43
  44 using namespace std;
  45
  46 TraceCPU::TraceCPU(const string &name,
  47                    MemInterface *icache_interface,
  48                    MemInterface *dcache_interface,
  49                    MemTraceReader *data_trace)
  50     : SimObject(name), icacheInterface(icache_interface),
  51       dcacheInterface(dcache_interface),
  52       dataTrace(data_trace), outstandingRequests(0), tickEvent(this)
  53 {
  54     assert(dcacheInterface);
  55     nextCycle = dataTrace->getNextReq(nextReq);
  56     tickEvent.schedule(0);
  57 }
  58
  59 void
  60 TraceCPU::tick()
  61 {
  62     assert(outstandingRequests >= 0);
  63     assert(outstandingRequests < 1000);
  64     int instReqs = 0;
  65     int dataReqs = 0;
  66
  67     while (nextReq && curTick >= nextCycle) {
  68         assert(nextReq->thread_num < 4 && "Not enough threads");
  69         if (nextReq->isInstRead() && icacheInterface) {
  70             if (icacheInterface->isBlocked())
  71                 break;
  72
  73             nextReq->time = curTick;
  74             if (nextReq->cmd == Squash) {
  75                 icacheInterface->squash(nextReq->asid);
  76             } else {
  77                 ++instReqs;
  78                 if (icacheInterface->doEvents()) {
  79                     nextReq->completionEvent =
  80                         new TraceCompleteEvent(nextReq, this);
  81                     icacheInterface->access(nextReq);
  82                 } else {
  83                     icacheInterface->access(nextReq);
  84                     completeRequest(nextReq);
  85                 }
  86             }
  87         } else {
  88             if (dcacheInterface->isBlocked())
  89                 break;
  90
  91             ++dataReqs;
  92             nextReq->time = curTick;
  93             if (dcacheInterface->doEvents()) {
  94                 nextReq->completionEvent =
  95                     new TraceCompleteEvent(nextReq, this);
  96                 dcacheInterface->access(nextReq);
  97             } else {
  98                 dcacheInterface->access(nextReq);
  99                 completeRequest(nextReq);
 100             }
 101
 102         }
 103         nextCycle = dataTrace->getNextReq(nextReq);
 104     }
 105
 106     if (!nextReq) {
 107         // No more requests to send. Finish trailing events and exit.
 108         if (mainEventQueue.empty()) {
 109             new SimExitEvent("Finshed Memory Trace");
 110         } else {
 111             tickEvent.schedule(mainEventQueue.nextEventTime() + 1);
 112         }
 113     } else {
 114         tickEvent.schedule(max(curTick + 1, nextCycle));
 115     }
 116 }
 117
 118 void
 119 TraceCPU::completeRequest(MemReqPtr& req)
 120 {
 121 }
 122
 123 void
 124 TraceCompleteEvent::process()
 125 {
 126     tester->completeRequest(req);
 127 }
 128
 129 const char *
 130 TraceCompleteEvent::description()
 131 {
 132     return "trace access complete";
 133 }
 134
 135 TraceCPU::TickEvent::TickEvent(TraceCPU *c)
 136     : Event(&mainEventQueue, CPU_Tick_Pri), cpu(c)
 137 {
 138 }
 139
 140 void
 141 TraceCPU::TickEvent::process()
 142 {
 143     cpu->tick();
 144 }
 145
 146 const char *
 147 TraceCPU::TickEvent::description()
 148 {
 149     return "TraceCPU tick event";
 150 }
 151
 152
 153
 154 BEGIN_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 155
 156     SimObjectParam<BaseMem *> icache;
 157     SimObjectParam<BaseMem *> dcache;
 158     SimObjectParam<MemTraceReader *> data_trace;
 159
 160 END_DECLARE_SIM_OBJECT_PARAMS(TraceCPU)
 161
 162 BEGIN_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 163
 164     INIT_PARAM_DFLT(icache, "instruction cache", NULL),
 165     INIT_PARAM_DFLT(dcache, "data cache", NULL),
 166     INIT_PARAM_DFLT(data_trace, "data trace", NULL)
 167
 168 END_INIT_SIM_OBJECT_PARAMS(TraceCPU)
 169
 170 CREATE_SIM_OBJECT(TraceCPU)
 171 {
 172     return new TraceCPU(getInstanceName(),
 173                         (icache) ? icache->getInterface() : NULL,
 174                         (dcache) ? dcache->getInterface() : NULL,
 175                         data_trace);
 176 }
 177
 178 REGISTER_SIM_OBJECT("TraceCPU", TraceCPU)
 179